From d5c2e058c24a05f78f857f5aa4f3727de3a7fa79 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 17 Jul 2016 16:20:52 +0200 Subject: Add testcase for issue #98 --- testsuite/gna/issue98/test_load.vhdl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 testsuite/gna/issue98/test_load.vhdl (limited to 'testsuite/gna/issue98/test_load.vhdl') diff --git a/testsuite/gna/issue98/test_load.vhdl b/testsuite/gna/issue98/test_load.vhdl new file mode 100644 index 000000000..9aefe7915 --- /dev/null +++ b/testsuite/gna/issue98/test_load.vhdl @@ -0,0 +1,31 @@ +library ieee ; +use ieee.std_logic_1164.all; + +entity test_load is + +port( + clk_i : in std_ulogic; + rst_i : in std_ulogic; + dat_i : in std_ulogic_vector(0 to 31); + sot_in : in std_ulogic; + dat_o : out std_ulogic_vector(0 to 2559) + + ); +end test_load; + +architecture RTL of test_load is + + signal w : std_ulogic_vector(0 to 2559); + +begin + + process(clk_i) + begin + if (clk_i'event and clk_i = '1') then + w <= dat_i & w(0 to 2559-32); + + end if; + end process; + dat_o <= w; + +end RTL; -- cgit v1.2.3