From 15f250b53c21dc9898126d9476edb4322cdbb6b4 Mon Sep 17 00:00:00 2001 From: Tristan Gingold <tgingold@free.fr> Date: Mon, 12 Jun 2017 05:38:52 +0200 Subject: Add reproducer for #301 --- testsuite/gna/issue301/packages/pkg_components.vhd | 194 +++++++++++++++++++++ testsuite/gna/issue301/packages/pkg_helper.vhd | 58 ++++++ testsuite/gna/issue301/packages/pkg_param.vhd | 78 +++++++++ .../gna/issue301/packages/pkg_param_derived.vhd | 73 ++++++++ testsuite/gna/issue301/packages/pkg_trellis.vhd | 185 ++++++++++++++++++++ testsuite/gna/issue301/packages/pkg_types.vhd | 37 ++++ 6 files changed, 625 insertions(+) create mode 100644 testsuite/gna/issue301/packages/pkg_components.vhd create mode 100644 testsuite/gna/issue301/packages/pkg_helper.vhd create mode 100644 testsuite/gna/issue301/packages/pkg_param.vhd create mode 100644 testsuite/gna/issue301/packages/pkg_param_derived.vhd create mode 100644 testsuite/gna/issue301/packages/pkg_trellis.vhd create mode 100644 testsuite/gna/issue301/packages/pkg_types.vhd (limited to 'testsuite/gna/issue301/packages') diff --git a/testsuite/gna/issue301/packages/pkg_components.vhd b/testsuite/gna/issue301/packages/pkg_components.vhd new file mode 100644 index 000000000..fc86159aa --- /dev/null +++ b/testsuite/gna/issue301/packages/pkg_components.vhd @@ -0,0 +1,194 @@ +--! +--! Copyright (C) 2011 - 2014 Creonic GmbH +--! +--! This file is part of the Creonic Viterbi Decoder, which is distributed +--! under the terms of the GNU General Public License version 2. +--! +--! @file +--! @brief Component declarations for Viterbi decoder +--! @author Markus Fehrenz +--! @date 2011/04/07 +--! +--! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library dec_viterbi; +use dec_viterbi.pkg_param.all; +use dec_viterbi.pkg_param_derived.all; +use dec_viterbi.pkg_types.all; + +package pkg_components is + + component axi4s_buffer is + generic ( + DATA_WIDTH : natural := 1 + ); + port ( + clk : in std_logic; + rst : in std_logic; + + input : in std_logic_vector(DATA_WIDTH - 1 downto 0); + input_valid : in std_logic; + input_last : in std_logic; + input_accept : out std_logic; + + output : out std_logic_vector(DATA_WIDTH - 1 downto 0); + output_valid : out std_logic; + output_last : out std_logic; + output_accept : in std_logic + ); + end component axi4s_buffer; + + component branch_distance is + generic( + EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0) + ); + port( + clk : in std_logic; + rst : in std_logic; + + s_axis_input_tvalid : in std_logic; + s_axis_input_tdata : in t_input_block; + s_axis_input_tlast : in std_logic; + s_axis_input_tready : out std_logic; + + m_axis_output_tvalid : out std_logic; + m_axis_output_tdata : out std_logic_vector(BW_BRANCH_RESULT - 1 downto 0); + m_axis_output_tlast : out std_logic; + m_axis_output_tready : in std_logic + + ); + end component branch_distance; + + component acs is + generic( + initialize_value : in signed(BW_MAX_PROBABILITY - 1 downto 0) + ); + port( + clk : in std_logic; + rst : in std_logic; + + s_axis_inbranch_tvalid : in std_logic; + s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0); + s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0); + s_axis_inbranch_tlast : in std_logic; + s_axis_inbranch_tready : out std_logic; + + s_axis_inprev_tvalid : in std_logic; + s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0); + s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0); + s_axis_inprev_tready : out std_logic; + + m_axis_outprob_tvalid : out std_logic; + m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0); + m_axis_outprob_tready : in std_logic; + + m_axis_outdec_tvalid : out std_logic; + m_axis_outdec_tdata : out std_logic; + m_axis_outdec_tlast : out std_logic; + m_axis_outdec_tready : in std_logic + ); + end component acs; + + component ram_ctrl is + port( + clk : in std_logic; + rst : in std_logic; + + s_axis_input_tvalid : in std_logic; + s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0); + s_axis_input_tlast : in std_logic; + s_axis_input_tready : out std_logic; + + m_axis_output_tvalid : out std_logic_vector(1 downto 0); + m_axis_output_tdata : out t_ram_rd_data; + m_axis_output_tlast : out std_logic_vector(1 downto 0); + m_axis_output_tready : in std_logic_vector(1 downto 0); + m_axis_output_window_tuser : out std_logic_vector(1 downto 0); + m_axis_output_last_tuser : out std_logic_vector(1 downto 0); + + s_axis_ctrl_tvalid : in std_logic; + s_axis_ctrl_tdata : in std_logic_vector(31 downto 0); + s_axis_ctrl_tready : out std_logic + ); + end component ram_ctrl; + + component generic_sp_ram is + generic( + DISTR_RAM : boolean; + WORDS : integer; + BITWIDTH : integer + ); + port( + clk : in std_logic; + rst : in std_logic; + + wen : in std_logic; + en : in std_logic; + + a : in std_logic_vector(BW_MAX_WINDOW_LENGTH - 1 downto 0); + d : in std_logic_vector(BITWIDTH - 1 downto 0 ); + q : out std_logic_vector(BITWIDTH - 1 downto 0) + ); + end component generic_sp_ram; + + component trellis_traceback is + port( + clk : in std_logic; + rst : in std_logic; + + s_axis_input_tvalid : in std_logic; + s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0); + s_axis_input_tlast : in std_logic; + s_axis_input_tready : out std_logic; + s_axis_input_window_tuser : in std_logic; + s_axis_input_last_tuser : in std_logic; + + m_axis_output_tvalid : out std_logic; + m_axis_output_tdata : out std_logic; + m_axis_output_tlast : out std_logic; + m_axis_output_last_tuser : out std_logic; + m_axis_output_tready : in std_logic + ); + end component trellis_traceback; + + component reorder is + port( + clk : in std_logic; + rst : in std_logic; + + s_axis_input_tvalid : in std_logic; + s_axis_input_tdata : in std_logic; + s_axis_input_tlast : in std_logic; + s_axis_input_last_tuser : in std_logic; + s_axis_input_tready : out std_logic; + + m_axis_output_tvalid : out std_logic; + m_axis_output_tdata : out std_logic; + m_axis_output_tlast : out std_logic; + m_axis_output_last_tuser : out std_logic; + m_axis_output_tready : in std_logic + ); + end component reorder; + + component recursionx is + port( + clk : in std_logic; + rst : in std_logic; + + s_axis_input_tvalid : in std_logic; + s_axis_input_tdata : in std_logic; + s_axis_input_tlast : in std_logic; + s_axis_input_tready : out std_logic; + + m_axis_output_tvalid : out std_logic; + m_axis_output_tdata : out std_logic; + m_axis_output_tlast : out std_logic; + m_axis_output_tready : in std_logic + ); + end component recursionx; + +end package pkg_components; diff --git a/testsuite/gna/issue301/packages/pkg_helper.vhd b/testsuite/gna/issue301/packages/pkg_helper.vhd new file mode 100644 index 000000000..8fe59743a --- /dev/null +++ b/testsuite/gna/issue301/packages/pkg_helper.vhd @@ -0,0 +1,58 @@ +--! +--! Copyright (C) 2011 - 2014 Creonic GmbH +--! +--! This file is part of the Creonic Viterbi Decoder, which is distributed +--! under the terms of the GNU General Public License version 2. +--! +--! @file +--! @brief Helper package with useful functions +--! @author Markus Fehrenz +--! @date 2011/12/02 +--! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +package pkg_helper is + + --! + --! Return the log_2 of an natural value, i.e. the number of bits required + --! to represent this unsigned value. + --! + function no_bits_natural(value_in : natural) return natural; + + --! Return maximum of two input values + function max(value_in_a, value_in_b : natural) return natural; + +end pkg_helper; + + +package body pkg_helper is + + function no_bits_natural(value_in: natural) return natural is + variable v_n_bit : unsigned(31 downto 0); + begin + if value_in = 0 then + return 0; + end if; + v_n_bit := to_unsigned(value_in, 32); + for i in 31 downto 0 loop + if v_n_bit(i) = '1' then + return i + 1; + end if; + end loop; + return 1; + end no_bits_natural; + + function max(value_in_a, value_in_b : natural) return natural is + begin + if value_in_a > value_in_b then + return value_in_a; + else + return value_in_b; + end if; + end function; + +end pkg_helper; diff --git a/testsuite/gna/issue301/packages/pkg_param.vhd b/testsuite/gna/issue301/packages/pkg_param.vhd new file mode 100644 index 000000000..1bc3f6602 --- /dev/null +++ b/testsuite/gna/issue301/packages/pkg_param.vhd @@ -0,0 +1,78 @@ +--! +--! Copyright (C) 2011 - 2014 Creonic GmbH +--! +--! This file is part of the Creonic Viterbi Decoder, which is distributed +--! under the terms of the GNU General Public License version 2. +--! +--! @file +--! @brief Parameters +--! @author Markus Fehrenz +--! @date 2011/07/01 +--! +--! @details This is the configuration file of the Viterbi decoder. +--! Any changes for parameters should be done here. +--! Changing parameters somewhere else may result in a malicious +--! behavior. +--! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +package pkg_param is + ----------------------------------- + -- Convolutional Code Parameters -- + ----------------------------------- + + + -- + -- Set the number of parity values + -- This has to correspond to PARITY_POLYNOMIALS + -- + constant NUMBER_PARITY_BITS : natural := 2; + type t_parity is array (NUMBER_PARITY_BITS - 1 downto 0) of natural; + + -- + -- Set parity polynoms in decimal notation + -- NUMBER_PARITY_BITS has to correspond to the number of elements + -- Examples: WiFi : [121,91] or [121,91,101] + -- CDMA : [491,369] or [367,435,369] or [501,441,331,315] + -- GSM : [27,19] or [27,21,31] + -- DAB : [91,121,101,91] + -- WiMAX: [91,121,117] + -- + constant PARITY_POLYNOMIALS : t_parity := (121,91); + + + -- + -- Set a recursive polynomial + -- Set to 0 if no recursion is used + -- Setting this arbitrary may result in a worse error correction ability + -- + constant FEEDBACK_POLYNOMIAL : natural := 0; + + + ----------------------------- + -- Architecture Parameters -- + ----------------------------- + + -- + -- Set bit width of LLR input + -- Recommended values: 3 or 4 + -- + constant BW_LLR_INPUT : natural := 4; + + -- + -- Set the maximum window length which shall be allowed at runtime. + -- Recommended: at least 6 * constraint length + -- + constant MAX_WINDOW_LENGTH : natural := 96; + + -- + -- Set to 'true' if distributed RAM shall be used + -- Set to 'false' if block RAM shall be used + -- + constant DISTRIBUTED_RAM : boolean := true; + +end package pkg_param; diff --git a/testsuite/gna/issue301/packages/pkg_param_derived.vhd b/testsuite/gna/issue301/packages/pkg_param_derived.vhd new file mode 100644 index 000000000..f6e77cada --- /dev/null +++ b/testsuite/gna/issue301/packages/pkg_param_derived.vhd @@ -0,0 +1,73 @@ +--! +--! Copyright (C) 2011 - 2014 Creonic GmbH +--! +--! This file is part of the Creonic Viterbi Decoder, which is distributed +--! under the terms of the GNU General Public License version 2. +--! +--! @file +--! @brief Derived parameters +--! @author Markus Fehrenz +--! @date 2011/07/04 +--! +--! @details This constants are derived from constants defined in pkg_param. +--! In order to prevent errors, there is no user choice for these parameters. +--! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library dec_viterbi; +use dec_viterbi.pkg_param.all; +use dec_viterbi.pkg_helper.all; + + +package pkg_param_derived is + + -- Calculation of constraint length. + function calc_constraint_length return natural; + + -- Memory depth of the encoder shift register. + constant ENCODER_MEMORY_DEPTH : natural; + + -- Number of trellis states corresponds to the nubmer of ACS units. + constant NUMBER_TRELLIS_STATES : natural; + + -- Number of branch units for a single polynomial set + constant NUMBER_BRANCH_UNITS : natural; + + -- Bitwidth constants are needed for type conversions + constant BW_TRELLIS_STATES : natural; + constant BW_MAX_WINDOW_LENGTH : natural; + constant BW_BRANCH_RESULT : natural; + constant BW_MAX_PROBABILITY : natural; + +end package pkg_param_derived; + + +package body pkg_param_derived is + + function calc_constraint_length return natural is + variable v_maximum : natural := 0; + begin + + -- Find the position of the leftmost bit in the polynomials. + for i in NUMBER_PARITY_BITS - 1 downto 0 loop + v_maximum := max(v_maximum, no_bits_natural(PARITY_POLYNOMIALS(i))); + end loop; + v_maximum := max(v_maximum, no_bits_natural(FEEDBACK_POLYNOMIAL)); + return v_maximum; + end function calc_constraint_length; + + + constant ENCODER_MEMORY_DEPTH : natural := calc_constraint_length - 1; + + constant NUMBER_TRELLIS_STATES : natural := 2 ** ENCODER_MEMORY_DEPTH; + + constant NUMBER_BRANCH_UNITS : natural := 2 ** NUMBER_PARITY_BITS; + + constant BW_TRELLIS_STATES : natural := no_bits_natural(NUMBER_TRELLIS_STATES - 1); + constant BW_MAX_WINDOW_LENGTH : natural := no_bits_natural(MAX_WINDOW_LENGTH - 1); + constant BW_BRANCH_RESULT : natural := no_bits_natural((2 ** (BW_LLR_INPUT - 1)) * NUMBER_PARITY_BITS) + 1; + constant BW_MAX_PROBABILITY : natural := no_bits_natural(((2 ** (BW_LLR_INPUT - 1)) * NUMBER_PARITY_BITS) * 4 * ENCODER_MEMORY_DEPTH); +end package body pkg_param_derived; diff --git a/testsuite/gna/issue301/packages/pkg_trellis.vhd b/testsuite/gna/issue301/packages/pkg_trellis.vhd new file mode 100644 index 000000000..a797d3ac9 --- /dev/null +++ b/testsuite/gna/issue301/packages/pkg_trellis.vhd @@ -0,0 +1,185 @@ +--! +--! Copyright (C) 2011 - 2014 Creonic GmbH +--! +--! This file is part of the Creonic Viterbi Decoder, which is distributed +--! under the terms of the GNU General Public License version 2. +--! +--! @file +--! @brief Trellis parameter calculations (e.g., transitions, init values). +--! @author Markus Fehrenz +--! @date 2011/07/27 +--! +--! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library dec_viterbi; +use dec_viterbi.pkg_param.all; +use dec_viterbi.pkg_param_derived.all; +use dec_viterbi.pkg_types.all; + + +package pkg_trellis is + + type t_prev_base is array (1 downto 0) of std_logic_vector(BW_TRELLIS_STATES - 1 downto 0); + type t_previous_states is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_prev_base; + + type t_trans_base is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0); + type t_transitions is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base; + + type t_trans_base_signed is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS downto 0); + type t_transitions_signed is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base_signed; + + + -- + -- This function calculates the previous states of each state. + -- The values are used to connect the ACS units. + -- + function calc_previous_states return t_previous_states; + + + -- + -- This function calculates corresponding transitions to a trellis sate. + -- The values are used to connect branch units to ACS units. + -- + function calc_transitions return t_transitions; + + + -- + -- This function calculates the initialization values for trellis metrics. + -- The values are used as a constant and written to the ACS unit, every time a new block arrives. + -- + function calc_initialize return t_node_s; + + constant PREVIOUS_STATES : t_previous_states; + constant TRANSITIONS : t_transitions; + constant INITIALIZE_TRELLIS : t_node_s; + +end package pkg_trellis; + + +package body pkg_trellis is + + + function calc_previous_states return t_previous_states is + variable v_prev_states : t_previous_states := (others=>(others=>(others => '0'))); + variable v_state0, v_state1 : std_logic_vector(BW_TRELLIS_STATES - 1 downto 0); + begin + for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop + v_state0 := std_logic_vector(to_unsigned(i,BW_TRELLIS_STATES)); + v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '0'; + v_prev_states(i)(0) := v_state1; + v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '1'; + v_prev_states(i)(1) := v_state1; + end loop; + return v_prev_states; + end function calc_previous_states; + + + function calc_transitions return t_transitions is + variable v_transitions : t_transitions_signed := (others => (others => (others => '0'))); + variable v_transitions_out : t_transitions := (others => (others => (others => '0'))); + variable v_one_transition : std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0); + variable v_next_state : unsigned(ENCODER_MEMORY_DEPTH - 1 downto 0) := (others => '0'); + variable v_state, v_states : unsigned(ENCODER_MEMORY_DEPTH downto 0); + variable v_bit : std_logic := '0'; + begin + + -- + -- It is possible to reduce code size at this stage, if feedback is handled differently, + -- but the complexity will increase. + -- + + for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop + + -- + -- for input : 0 + -- determine correct input with feedback + -- + v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH); + for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop + v_bit := v_bit xor v_next_state(k); + end loop; + v_state(ENCODER_MEMORY_DEPTH) := v_bit; + v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH); + v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1); + v_bit := '0'; + + -- determine paritybits + for j in NUMBER_PARITY_BITS - 1 downto 0 loop + v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1); + for k in ENCODER_MEMORY_DEPTH downto 0 loop + v_bit := v_bit xor v_states(k); + end loop; + v_one_transition(j) := v_bit; + v_bit := '0'; + end loop; + + -- decide where to save the parity result + if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then + v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1'; + v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition; + else + v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition; + end if; + + -- + -- for input: 1 + -- determine correct input with feedback + -- + v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH); + for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop + v_bit := v_bit xor v_next_state(k); + end loop; + v_state(ENCODER_MEMORY_DEPTH) := '1' xor v_bit; + v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH); + v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1); + v_bit := '0'; + + -- determine paritybits + for j in NUMBER_PARITY_BITS - 1 downto 0 loop + v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1); + for k in ENCODER_MEMORY_DEPTH downto 0 loop + v_bit := v_bit xor v_states(k); + end loop; + v_one_transition(j) := v_bit; + v_bit := '0'; + end loop; + + -- decide where to save parity result + if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then + v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1'; + v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition; + else + v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition; + end if; + end loop; + + -- truncate, the bit, used to decide where to save parity result + for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop + v_transitions_out(i)(1) := v_transitions(i)(1)(NUMBER_PARITY_BITS - 1 downto 0); + v_transitions_out(i)(0) := v_transitions(i)(0)(NUMBER_PARITY_BITS - 1 downto 0); + end loop; + + return v_transitions_out; + end function calc_transitions; + + + function calc_initialize return t_node_s is + variable v_initialize : t_node_s; + begin + v_initialize(0) := to_signed(0, BW_MAX_PROBABILITY); + for i in NUMBER_TRELLIS_STATES - 1 downto 1 loop + v_initialize(i) := to_signed(- 2 ** (BW_MAX_PROBABILITY - 2), BW_MAX_PROBABILITY); + end loop; + return v_initialize; + end function calc_initialize; + + + constant PREVIOUS_STATES : t_previous_states := calc_previous_states; + constant TRANSITIONS : t_transitions := calc_transitions; + constant INITIALIZE_TRELLIS : t_node_s := calc_initialize; + +end package body pkg_trellis; diff --git a/testsuite/gna/issue301/packages/pkg_types.vhd b/testsuite/gna/issue301/packages/pkg_types.vhd new file mode 100644 index 000000000..5acdd4ebe --- /dev/null +++ b/testsuite/gna/issue301/packages/pkg_types.vhd @@ -0,0 +1,37 @@ +--! +--! Copyright (C) 2011 - 2014 Creonic GmbH +--! +--! This file is part of the Creonic Viterbi Decoder, which is distributed +--! under the terms of the GNU General Public License version 2. +--! +--! @file +--! @brief Global types for the Viterbi decoder +--! @author Markus Fehrenz +--! @date 2011/07/04 +--! +--! @details Most types are shared and used in different context. +--! Changing single types should be done with adding an additional type. +--! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library dec_viterbi; +use dec_viterbi.pkg_param.all; +use dec_viterbi.pkg_param_derived.all; + +package pkg_types is + + -- Parity structure: p1_bit, p2_bit, ..., pN_bit + type t_input_block is array (NUMBER_PARITY_BITS - 1 downto 0) of signed(BW_LLR_INPUT - 1 downto 0); + + -- Types are used for bulk information to ACS and branch unit. + type t_node_s is array (NUMBER_TRELLIS_STATES - 1 downto 0) of signed(BW_MAX_PROBABILITY - 1 downto 0); + type t_node is array (NUMBER_TRELLIS_STATES - 1 downto 0) of std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0); + type t_branch is array (NUMBER_BRANCH_UNITS - 1 downto 0) of std_logic_vector(BW_BRANCH_RESULT - 1 downto 0); + + -- RAM Data + type t_ram_rd_data is array (1 downto 0) of std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0); + +end package pkg_types; -- cgit v1.2.3