From fbd853c88b4b1c3008b1b39882ac2b99b6e59460 Mon Sep 17 00:00:00 2001 From: Tristan Gingold <tgingold@free.fr> Date: Fri, 5 Nov 2021 19:04:25 +0100 Subject: testsuite/gna: add a test for #1908 --- testsuite/gna/issue1908/ini_pkg.vhdl | 36 ++++ testsuite/gna/issue1908/map_synchro.vhdl | 198 ++++++++++++++++++++++ testsuite/gna/issue1908/sr_synchronizer.vhdl | 89 ++++++++++ testsuite/gna/issue1908/test_9_tb.vhdl | 239 +++++++++++++++++++++++++++ testsuite/gna/issue1908/testsuite.sh | 11 ++ 5 files changed, 573 insertions(+) create mode 100644 testsuite/gna/issue1908/ini_pkg.vhdl create mode 100644 testsuite/gna/issue1908/map_synchro.vhdl create mode 100644 testsuite/gna/issue1908/sr_synchronizer.vhdl create mode 100644 testsuite/gna/issue1908/test_9_tb.vhdl create mode 100755 testsuite/gna/issue1908/testsuite.sh (limited to 'testsuite/gna/issue1908') diff --git a/testsuite/gna/issue1908/ini_pkg.vhdl b/testsuite/gna/issue1908/ini_pkg.vhdl new file mode 100644 index 000000000..0ed8d9642 --- /dev/null +++ b/testsuite/gna/issue1908/ini_pkg.vhdl @@ -0,0 +1,36 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +----------------------------------------------------------------------------------- +-- * Package +----------------------------------------------------------------------------------- +package ini_pkg is + ----------------------------------------------------------------------------------- + -- * Types + ----------------------------------------------------------------------------------- + -- With the following values no bug ocurred + type ini_t is record + val_of_0 : std_logic; + val_of_1 : std_logic; + val_of_2 : std_logic; + val_of_3 : std_logic; + val_of_4 : std_logic; + val_of_5 : std_logic; + end record; + + -- With the following values a an exception rise in GHDL, printing the GHDL Bug Ocurred Message + -- type ini_t is record + -- vval_of_0 : std_logic; + -- val_of_1 : std_logic; + -- val_of_2 : std_logic; + -- val_of_3 : std_logic; + -- val_of_4 : std_logic; + -- val_of_5 : std_logic; + -- end record; + + +----------------------------------------------------------------------------------- +-- * End Package +----------------------------------------------------------------------------------- +end package ini_pkg; + diff --git a/testsuite/gna/issue1908/map_synchro.vhdl b/testsuite/gna/issue1908/map_synchro.vhdl new file mode 100644 index 000000000..17a0f3abe --- /dev/null +++ b/testsuite/gna/issue1908/map_synchro.vhdl @@ -0,0 +1,198 @@ +----------------------------------------------------------------------------------- +-- * Libs +----------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY WORK; +USE WORK.ini_pkg.all; + +----------------------------------------------------------------------------------- +-- * Entity +----------------------------------------------------------------------------------- +ENTITY map_synchro IS + PORT ( + CLK_I : in std_logic; + RSTN_I : in std_logic; + + A_val_of_0 : in std_logic; + A_val_of_1 : in std_logic; + A_val_of_2 : in std_logic; + A_val_of_3 : in std_logic; + A_val_of_4 : in std_logic; + A_val_of_5 : in std_logic; + A_SYNC_O : out ini_t; + + B_val_of_0 : in std_logic; + B_val_of_1 : in std_logic; + B_val_of_2 : in std_logic; + B_val_of_3 : in std_logic; + B_val_of_4 : in std_logic; + B_val_of_5 : in std_logic; + B_SYNC_O : out ini_t + + ); +END map_synchro; +----------------------------------------------------------------------------------- +-- * Architecture Begins +----------------------------------------------------------------------------------- +ARCHITECTURE structure OF map_synchro IS + ----------------------------------------------------------------------------------- + -- * Components Declaration + ----------------------------------------------------------------------------------- + component sr_synchronizer is + generic ( + G_INIT : std_logic := '0'; -- Reset value + G_STAGES : natural := 2 -- Number of synchronization stages + ); + port ( + CLK_I : in std_logic; + RSTN_I : in std_logic; + + X_I : in std_logic; + X_SYNC_O : out std_logic + ); + end component sr_synchronizer; + + ----------------------------------------------------------------------------------- + -- * Signals + ----------------------------------------------------------------------------------- + -- With the following values a an exception rise in GHDL, printing the GHDL Bug Ocurred Message + signal s_a_sync_o : std_logic; + signal s_b_sync_o : std_logic; + + -- With the following values no bug ocurred + -- signal s_a_sync_o : ini_t; + -- signal s_b_sync_o : ini_t; + + +----------------------------------------------------------------------------------- +-- * Architecture structure +----------------------------------------------------------------------------------- +BEGIN + ----------------------------------------------------------------------------------- + -- * Mapping IO + ----------------------------------------------------------------------------------- + A_SYNC_O <= s_a_sync_o; + B_SYNC_O <= s_b_sync_o; + + ----------------------------------------------------------------------------------- + -- * Components Instatiation + ----------------------------------------------------------------------------------- + -- ** 6 Synchronizers for A + ----------------------------------------------------------------------------------- + a_synchronizer_0: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => A_val_of_0, + X_SYNC_O => s_a_sync_o.val_of_0 + ); + + a_synchronizer_1: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => A_val_of_1, + X_SYNC_O => s_a_sync_o.val_of_1 + ); + + a_synchronizer_2: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => A_val_of_2, + X_SYNC_O => s_a_sync_o.val_of_2 + ); + + a_synchronizer_3: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => A_val_of_3, + X_SYNC_O => s_a_sync_o.val_of_3 + ); + + a_synchronizer_4: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => A_val_of_4, + X_SYNC_O => s_a_sync_o.val_of_4 + ); + + a_synchronizer_5: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => A_val_of_5, + X_SYNC_O => s_a_sync_o.val_of_5 + ); + + -- ** 6 Synchronizers for B + ----------------------------------------------------------------------------------- + b_synchronizer_0: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => B_val_of_0, + X_SYNC_O => s_b_sync_o.val_of_0 + ); + + b_synchronizer_1: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => B_val_of_1, + X_SYNC_O => s_b_sync_o.val_of_1 + ); + + b_synchronizer_2: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => B_val_of_2, + X_SYNC_O => s_b_sync_o.val_of_2 + ); + + b_synchronizer_3: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => B_val_of_3, + X_SYNC_O => s_b_sync_o.val_of_3 + ); + + b_synchronizer_4: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => B_val_of_4, + X_SYNC_O => s_b_sync_o.val_of_4 + ); + + b_synchronizer_5: sr_synchronizer + port map ( + CLK_I => CLK_I, + RSTN_I => RSTN_I, + + X_I => B_val_of_5, + X_SYNC_O => s_b_sync_o.val_of_5 + ); + +----------------------------------------------------------------------------------- +-- * Architecture Ends +----------------------------------------------------------------------------------- +END structure; diff --git a/testsuite/gna/issue1908/sr_synchronizer.vhdl b/testsuite/gna/issue1908/sr_synchronizer.vhdl new file mode 100644 index 000000000..d0afc900f --- /dev/null +++ b/testsuite/gna/issue1908/sr_synchronizer.vhdl @@ -0,0 +1,89 @@ + +----------------------------------------------------------------------------------- +-- * Libs +----------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +----------------------------------------------------------------------------------- +-- * Entity +----------------------------------------------------------------------------------- +ENTITY sr_synchronizer IS + GENERIC ( + G_INIT : std_logic := '0'; -- Reset value + G_STAGES : natural := 2 -- Number of synchronization stages + ); + PORT ( + CLK_I : in std_logic; + RSTN_I : in std_logic; + + X_I : in std_logic; + X_SYNC_O : out std_logic + ); +END sr_synchronizer; + +----------------------------------------------------------------------------------- +-- * Architecture Begins +----------------------------------------------------------------------------------- +ARCHITECTURE synthetizable OF sr_synchronizer IS + ----------------------------------------------------------------------------------- + -- * Types + ----------------------------------------------------------------------------------- + type shift_regsiter_t is array (G_STAGES-1 downto 0) of std_logic; + + ----------------------------------------------------------------------------------- + -- * Signals + ----------------------------------------------------------------------------------- + signal r_rst_cnt : natural range 0 to G_STAGES; -- To reset the shift-register stages + signal r_x_sync_o : shift_regsiter_t; -- Shift register + signal s_x_i : std_logic; + +----------------------------------------------------------------------------------- +-- * Architecture synthetizable +----------------------------------------------------------------------------------- +BEGIN + ----------------------------------------------------------------------------------- + -- * Generics Constraints Checking + ----------------------------------------------------------------------------------- + assert(G_INIT='0' or G_INIT='1') + report "-ERROR- In 'sr_synchronizer' component, the generic parameter 'G_INIT' is bad defined." & + " Must be '1' or '0' of std_logic type." severity failure; + + assert(G_STAGES > 0) + report "-ERROR- In 'sr_synchronizer' component, the generic parameter 'G_STAGES' is bad defined." & + " Must be 1 at least." severity failure; + + ----------------------------------------------------------------------------------- + -- * Mapping IO + ----------------------------------------------------------------------------------- + X_SYNC_O <= r_x_sync_o(r_x_sync_o'high); + s_x_i <= X_I; + + ----------------------------------------------------------------------------------- + -- * Process + ----------------------------------------------------------------------------------- + -- ** Shift Register + ----------------------------------------------------------------------------------- + shift_register: process(CLK_I) + begin + if rising_edge(CLK_I) then + if RSTN_I='0' then + r_rst_cnt <= G_STAGES; -- Reset value of reset counter + else + if r_rst_cnt=0 then -- In case all shift register stages has performed + r_x_sync_o <= -- reset, change shift register input to 's_x_i' + r_x_sync_o(r_x_sync_o'high-1 downto r_x_sync_o'low) & s_x_i; -- value + else + r_rst_cnt <= r_rst_cnt-1; -- In case not all shift register stages has performed + r_x_sync_o <= -- reset, change shift register input to 'G_INIT' + r_x_sync_o(r_x_sync_o'high-1 downto r_x_sync_o'low) & G_INIT; -- value and, decrement reset counter value + end if; + end if; -- RSTN_I + end if; -- rising_edge(CLK_I) + end process; + +----------------------------------------------------------------------------------- +-- * Architecture Ends +----------------------------------------------------------------------------------- +END synthetizable; diff --git a/testsuite/gna/issue1908/test_9_tb.vhdl b/testsuite/gna/issue1908/test_9_tb.vhdl new file mode 100644 index 000000000..a698112b3 --- /dev/null +++ b/testsuite/gna/issue1908/test_9_tb.vhdl @@ -0,0 +1,239 @@ +----------------------------------------------------------------------------------- +-- * Libs +----------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; +USE STD.ENV.FINISH; -- use of vhdl-2008 + +LIBRARY WORK; +USE WORK.ini_pkg.all; + +----------------------------------------------------------------------------------- +-- * Entity +----------------------------------------------------------------------------------- +ENTITY test_9_tb IS +END test_9_tb; + +----------------------------------------------------------------------------------- +-- * Architecture Begins +----------------------------------------------------------------------------------- +ARCHITECTURE str_tb OF test_9_tb IS + ----------------------------------------------------------------------------------- + -- * Constants + ----------------------------------------------------------------------------------- + constant C_CLK_PERIOD : time := 20 ns; -- 50 Mhz + + ----------------------------------------------------------------------------------- + -- * Components Declaration + ----------------------------------------------------------------------------------- + component map_synchro is + port ( + CLK_I : in std_logic; + RSTN_I : in std_logic; + + A_val_of_0 : in std_logic; + A_val_of_1 : in std_logic; + A_val_of_2 : in std_logic; + A_val_of_3 : in std_logic; + A_val_of_4 : in std_logic; + A_val_of_5 : in std_logic; + A_SYNC_O : out ini_t; + + B_val_of_0 : in std_logic; + B_val_of_1 : in std_logic; + B_val_of_2 : in std_logic; + B_val_of_3 : in std_logic; + B_val_of_4 : in std_logic; + B_val_of_5 : in std_logic; + B_SYNC_O : out ini_t + + ); + end component map_synchro; + + + ----------------------------------------------------------------------------------- + -- * Signals + ----------------------------------------------------------------------------------- + -- ** Structure (Interconnections) + ----------------------------------------------------------------------------------- + signal s_b_sync : ini_t; + signal s_a_sync : ini_t; + + -- ** Stimulus + ----------------------------------------------------------------------------------- + signal s_clk : std_logic := '1'; + signal s_rstn : std_logic := '0'; + + signal s_a_val_of_0 : std_logic ; + signal s_a_val_of_1 : std_logic ; + signal s_a_val_of_2 : std_logic ; + signal s_a_val_of_3 : std_logic ; + signal s_a_val_of_4 : std_logic ; + signal s_a_val_of_5 : std_logic ; + + signal s_b_val_of_0 : std_logic ; + signal s_b_val_of_1 : std_logic ; + signal s_b_val_of_2 : std_logic ; + signal s_b_val_of_3 : std_logic ; + signal s_b_val_of_4 : std_logic ; + signal s_b_val_of_5 : std_logic ; + + ----------------------------------------------------------------------------------- + -- * Procedures + ----------------------------------------------------------------------------------- + -- ** Initialize Boot Fallback Signals (PG and N_FAIL) + ----------------------------------------------------------------------------------- + procedure p_ini_signals ( + signal clk : in std_logic; + + signal a_val_of_0 : out std_logic; + signal a_val_of_1 : out std_logic; + signal a_val_of_2 : out std_logic; + signal a_val_of_3 : out std_logic; + signal a_val_of_4 : out std_logic; + signal a_val_of_5 : out std_logic; + + signal b_val_of_0 : out std_logic; + signal b_val_of_1 : out std_logic; + signal b_val_of_2 : out std_logic; + signal b_val_of_3 : out std_logic; + signal b_val_of_4 : out std_logic; + signal b_val_of_5 : out std_logic + ) is + begin + + + wait until rising_edge(clk); + a_val_of_0 <= '1'; + wait until rising_edge(clk); + a_val_of_1 <= '1'; + wait until rising_edge(clk); + a_val_of_2 <= '1'; + wait until rising_edge(clk); + a_val_of_3 <= '1'; + wait until rising_edge(clk); + a_val_of_4 <= '1'; + wait until rising_edge(clk); + a_val_of_5 <= '1'; + + wait until rising_edge(clk); + b_val_of_0 <= '1'; + wait until rising_edge(clk); + b_val_of_1 <= '1'; + wait until rising_edge(clk); + b_val_of_2 <= '1'; + wait until rising_edge(clk); + b_val_of_3 <= '1'; + wait until rising_edge(clk); + b_val_of_4 <= '1'; + wait until rising_edge(clk); + b_val_of_5 <= '1'; + + + wait until rising_edge(clk); + + end procedure p_ini_signals; + + + ----------------------------------------------------------------------------------- + -- * Architecture Structure Testbench + ----------------------------------------------------------------------------------- +BEGIN + ----------------------------------------------------------------------------------- + -- * Clock and Reset generation + ----------------------------------------------------------------------------------- + clk_gen: + s_clk <= not s_clk after C_CLK_PERIOD/2; + + rst_gen : + s_rstn <= + '1' after (1 us); + + ----------------------------------------------------------------------------------- + -- * Process + ----------------------------------------------------------------------------------- + -- ** Stimulus + ----------------------------------------------------------------------------------- + stimulus: process + -- + Procedures + procedure ini_signals ( + signal clk : in std_logic + ) is + begin + p_ini_signals ( + clk => clk , + + a_val_of_0 => s_a_val_of_0, + a_val_of_1 => s_a_val_of_1, + a_val_of_2 => s_a_val_of_2, + a_val_of_3 => s_a_val_of_3, + a_val_of_4 => s_a_val_of_4, + a_val_of_5 => s_a_val_of_5, + + b_val_of_0 => s_b_val_of_0, + b_val_of_1 => s_b_val_of_1, + b_val_of_2 => s_b_val_of_2, + b_val_of_3 => s_b_val_of_3, + b_val_of_4 => s_b_val_of_4, + b_val_of_5 => s_b_val_of_5 + ); + + end procedure ini_signals; + + + -- + Process begin + begin + + wait until s_rstn='1'; + write(output, LF & " ===========================================" & LF + & " +-- Starting Test 9 --+" & LF + & " ===========================================" & LF & LF); + + --================================================================================= + + ini_signals(s_clk); + + --================================================================================= + + write(output, LF & " +-- Test 9 has finished sucessfully!!" & LF); + write(output, LF & " ===========================================" & LF + & " +-- Finishing Test 9 --+" & LF + & " ===========================================" & LF & LF); + finish; + end process; + + ----------------------------------------------------------------------------------- + -- * Components Instatiation + ----------------------------------------------------------------------------------- + dut_0_boot_fallback: map_synchro + port map ( + CLK_I => s_clk, + RSTN_I => s_rstn, + + -- N_FAIL board signals + A_val_of_0 => s_a_val_of_0 , + A_val_of_1 => s_a_val_of_1 , + A_val_of_2 => s_a_val_of_2 , + A_val_of_3 => s_a_val_of_3 , + A_val_of_4 => s_a_val_of_4 , + A_val_of_5 => s_a_val_of_5 , + A_SYNC_O => s_a_sync , + + -- PG board signals + B_val_of_0 => s_b_val_of_0 , + B_val_of_1 => s_b_val_of_1 , + B_val_of_2 => s_b_val_of_2 , + B_val_of_3 => s_b_val_of_3 , + B_val_of_4 => s_b_val_of_4 , + B_val_of_5 => s_b_val_of_5 , + B_SYNC_O => s_b_sync + ); + +----------------------------------------------------------------------------------- +-- * Architecture Ends +----------------------------------------------------------------------------------- +END str_tb; diff --git a/testsuite/gna/issue1908/testsuite.sh b/testsuite/gna/issue1908/testsuite.sh new file mode 100755 index 000000000..b710460eb --- /dev/null +++ b/testsuite/gna/issue1908/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +$GHDL -i $GHDL_STD_FLAGS ini_pkg.vhdl sr_synchronizer.vhdl map_synchro.vhdl test_9_tb.vhdl +$GHDL -m --expect-failure $GHDL_STD_FLAGS test_9_tb + +clean + +echo "Test successful" -- cgit v1.2.3