From d3f4d087a5b572e53e37dd4154b4e9e7fab119c4 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 16 Nov 2022 19:44:02 +0100 Subject: testsuite/gna: add a test and close #1486 --- testsuite/gna/issue1486/testcasestatic.vhdl | 38 +++++++++++++++++++++++++++++ testsuite/gna/issue1486/testsuite.sh | 10 ++++++++ 2 files changed, 48 insertions(+) create mode 100644 testsuite/gna/issue1486/testcasestatic.vhdl create mode 100755 testsuite/gna/issue1486/testsuite.sh (limited to 'testsuite/gna/issue1486') diff --git a/testsuite/gna/issue1486/testcasestatic.vhdl b/testsuite/gna/issue1486/testcasestatic.vhdl new file mode 100644 index 000000000..873e88f69 --- /dev/null +++ b/testsuite/gna/issue1486/testcasestatic.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.ALL; + +entity TestcaseStatic is + port ( + SEL : in std_logic_vector(1 downto 0); + DATA0 : in std_logic_vector(7 downto 0); + DATA1 : in std_logic_vector(7 downto 0); + DATA2 : in std_logic_vector(7 downto 0); + DATA3 : in std_logic_vector(7 downto 0); + RESULT : out std_logic_vector(7 downto 0) + ); +end; + +architecture test of TestcaseStatic is + + constant SEL_ZERO : std_logic_vector(1 downto 0) := "00"; + +begin + + process(SEL, DATA0, DATA1, DATA2, DATA3) + begin + case (SEL) is + when SEL_ZERO => + RESULT <= DATA0; + when std_logic_vector(unsigned(SEL_ZERO)+1) => + RESULT <= DATA1; + when std_logic_vector(unsigned(SEL_ZERO)+2) => + RESULT <= DATA2; + when std_logic_vector(unsigned(SEL_ZERO)+3) => + RESULT <= DATA3; + when others => + RESULT <= (others => 'X'); + end case; + end process; + +end test; diff --git a/testsuite/gna/issue1486/testsuite.sh b/testsuite/gna/issue1486/testsuite.sh new file mode 100755 index 000000000..e97e4df71 --- /dev/null +++ b/testsuite/gna/issue1486/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze testcasestatic.vhdl + +clean + +echo "Test successful" -- cgit v1.2.3