From b623f87a6143ea71277969d79de7bd6a92443b93 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 4 Aug 2020 18:46:57 +0200 Subject: testsuite/gna: add a test for #1420 --- testsuite/gna/issue1420/repro1.vhdl | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 testsuite/gna/issue1420/repro1.vhdl (limited to 'testsuite/gna/issue1420/repro1.vhdl') diff --git a/testsuite/gna/issue1420/repro1.vhdl b/testsuite/gna/issue1420/repro1.vhdl new file mode 100644 index 000000000..f661f1e4d --- /dev/null +++ b/testsuite/gna/issue1420/repro1.vhdl @@ -0,0 +1,25 @@ +entity repro1 is +end entity; + +architecture tb of repro1 is + + type t_av_st is record + data : bit_vector; -- src -> sink + valid : bit; -- src -> sink + empty : bit_vector; -- src -> sink + chnnl : bit_vector; -- src -> sink + end record t_av_st; + type t_arr_av_st is array (NATURAL range <>) of t_av_st; + + constant C_VC_SOURCES : positive := 3; + constant C_VC_SINKS : positive := 3; + subtype vc_sources_range is natural range C_VC_SOURCES downto 1; + subtype vc_sinks_range is natural range C_VC_SINKS downto 1; + signal avst_snk : t_arr_av_st(vc_sinks_range)(data(8 downto 0), empty(0 downto 0), chnnl(0 downto 0)); + signal avst_src : t_arr_av_st(vc_sources_range)(data(8 downto 0), empty(0 downto 0), chnnl(0 downto 0)); + signal sink_sel : bit_vector(C_VC_SOURCES downto 1); + signal source_sel : bit_vector(C_VC_SINKS downto 1); + +begin + +end architecture tb; -- cgit v1.2.3