From 5428d6e8537dbe4b9533a29b5d8124340471cb4c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 1 Feb 2020 17:18:13 +0100
Subject: testsuite/gna: add a test for #1123

---
 testsuite/gna/issue1123/b1.vhdl | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 testsuite/gna/issue1123/b1.vhdl

(limited to 'testsuite/gna/issue1123/b1.vhdl')

diff --git a/testsuite/gna/issue1123/b1.vhdl b/testsuite/gna/issue1123/b1.vhdl
new file mode 100644
index 000000000..479da960f
--- /dev/null
+++ b/testsuite/gna/issue1123/b1.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity A is
+port(x: in std_ulogic_vector(4 downto 0));
+end entity;
+
+architecture test of A is
+begin
+end architecture;
+
+entity B is
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture test of B is
+    function to_vector(d: unsigned(4 downto 0)) return std_ulogic_vector is
+    begin
+        return std_ulogic_vector(d);
+    end function;
+
+    signal s: unsigned(4 downto 0) := (others => '0');
+begin
+    test: entity work.A
+    port map(
+        x => to_vector(s)
+    );
+end architecture;
-- 
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