From d8a81db96f512c0d58b554df294f4acb0915d6a9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 22 Jul 2020 06:57:46 +0200
Subject: vhdl: replace base_type with parent_type in nodes
Only for subtype definition and remove base_type in type definitions.
Allows to better track the addition of contraints.
---
src/synth/synth-aggr.adb | 1 +
src/vhdl/simulate/simul-environments.adb | 1 +
src/vhdl/vhdl-disp_tree.adb | 1 +
src/vhdl/vhdl-evaluation.adb | 12 +-
src/vhdl/vhdl-ieee-numeric.adb | 1 +
src/vhdl/vhdl-ieee-std_logic_1164.adb | 1 +
src/vhdl/vhdl-ieee-vital_timing.adb | 2 +-
src/vhdl/vhdl-nodes.adb | 17 +-
src/vhdl/vhdl-nodes.adb.in | 1 -
src/vhdl/vhdl-nodes.ads | 51 +--
src/vhdl/vhdl-nodes_meta.adb | 684 +++++++++++++++----------------
src/vhdl/vhdl-nodes_meta.ads | 4 +-
src/vhdl/vhdl-sem_assocs.adb | 4 +-
src/vhdl/vhdl-sem_decls.adb | 2 -
src/vhdl/vhdl-sem_expr.adb | 3 +-
src/vhdl/vhdl-sem_names.adb | 4 +-
src/vhdl/vhdl-sem_types.adb | 38 +-
src/vhdl/vhdl-std_package.adb | 39 +-
src/vhdl/vhdl-utils.adb | 49 ++-
src/vhdl/vhdl-utils.ads | 8 +-
20 files changed, 431 insertions(+), 492 deletions(-)
(limited to 'src')
diff --git a/src/synth/synth-aggr.adb b/src/synth/synth-aggr.adb
index 6177c106d..7732744a1 100644
--- a/src/synth/synth-aggr.adb
+++ b/src/synth/synth-aggr.adb
@@ -25,6 +25,7 @@ with Netlists.Utils; use Netlists.Utils;
with Netlists.Builders; use Netlists.Builders;
with Vhdl.Errors; use Vhdl.Errors;
+with Vhdl.Utils; use Vhdl.Utils;
with Synth.Errors; use Synth.Errors;
with Synth.Expr; use Synth.Expr;
diff --git a/src/vhdl/simulate/simul-environments.adb b/src/vhdl/simulate/simul-environments.adb
index 221e812d7..5e28441cf 100644
--- a/src/vhdl/simulate/simul-environments.adb
+++ b/src/vhdl/simulate/simul-environments.adb
@@ -22,6 +22,7 @@ with GNAT.Debug_Utilities;
with Simple_IO;
with Name_Table;
+with Vhdl.Utils; use Vhdl.Utils;
with Simul.Debugger; use Simul.Debugger;
package body Simul.Environments is
diff --git a/src/vhdl/vhdl-disp_tree.adb b/src/vhdl/vhdl-disp_tree.adb
index b9801ce89..06a06d640 100644
--- a/src/vhdl/vhdl-disp_tree.adb
+++ b/src/vhdl/vhdl-disp_tree.adb
@@ -25,6 +25,7 @@ with Files_Map;
with PSL.Types; use PSL.Types;
with PSL.Dump_Tree;
with Vhdl.Nodes_Meta;
+with Vhdl.Utils; use Vhdl.Utils;
-- Do not add a use clause for iirs_utils, as it may crash for ill-formed
-- trees, which is annoying while debugging.
diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb
index d21288136..65fa9e6ec 100644
--- a/src/vhdl/vhdl-evaluation.adb
+++ b/src/vhdl/vhdl-evaluation.adb
@@ -392,7 +392,7 @@ package body Vhdl.Evaluation is
Error_Kind ("create_range_subtype_by_length", A_Type);
end case;
Set_Location (Res, Loc);
- Set_Base_Type (Res, Get_Base_Type (A_Type));
+ Set_Parent_Type (Res, A_Type);
Set_Type_Staticness (Res, Locally);
return Res;
@@ -1199,18 +1199,20 @@ package body Vhdl.Evaluation is
Get_Range_Constraint (Left_Index);
Ret_Type : constant Iir :=
Get_Return_Type (Get_Implementation (Orig));
+ Rng_Type : constant Iir := Get_Index_Type (Ret_Type, 0);
A_Range : Iir;
Index_Type : Iir;
begin
A_Range := Create_Iir (Iir_Kind_Range_Expression);
- Set_Type (A_Range, Get_Index_Type (Ret_Type, 0));
+ Location_Copy (A_Range, Orig);
+ Set_Type (A_Range, Rng_Type);
Set_Expr_Staticness (A_Range, Locally);
Set_Left_Limit (A_Range, Get_Left_Limit (Left_Range));
Set_Direction (A_Range, Get_Direction (Left_Range));
- Location_Copy (A_Range, Orig);
Set_Right_Limit_By_Length (A_Range, Int64 (Res_Len));
+
Index_Type := Create_Range_Subtype_From_Type
- (Left_Index, Get_Location (Orig));
+ (Rng_Type, Get_Location (Orig));
Set_Range_Constraint (Index_Type, A_Range);
Res_Type := Create_Unidim_Array_From_Index
(Origin_Type, Index_Type, Orig);
@@ -2350,7 +2352,7 @@ package body Vhdl.Evaluation is
Index_Type := Create_Iir (Iir_Kind_Integer_Subtype_Definition);
Location_Copy (Index_Type, Conv);
Set_Range_Constraint (Index_Type, Rng);
- Set_Base_Type (Index_Type, Get_Base_Type (Conv_Index_Type));
+ Set_Parent_Type (Index_Type, Conv_Index_Type);
Set_Type_Staticness (Index_Type, Locally);
end if;
Res_Type := Create_Unidim_Array_From_Index
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index db368c380..a6a0559e4 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -21,6 +21,7 @@ with Vhdl.Std_Package;
with Std_Names; use Std_Names;
with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Ieee.Std_Logic_1164;
+with Vhdl.Utils; use Vhdl.Utils;
package body Vhdl.Ieee.Numeric is
type Pkg_Kind is (Pkg_Std, Pkg_Bit);
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 44fc5f631..ca962d2f5 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -19,6 +19,7 @@ with Types; use Types;
with Name_Table;
with Std_Names; use Std_Names;
with Vhdl.Errors; use Vhdl.Errors;
+with Vhdl.Utils; use Vhdl.Utils;
with Vhdl.Std_Package;
package body Vhdl.Ieee.Std_Logic_1164 is
diff --git a/src/vhdl/vhdl-ieee-vital_timing.adb b/src/vhdl/vhdl-ieee-vital_timing.adb
index 89cfc7df0..5650d4fdd 100644
--- a/src/vhdl/vhdl-ieee-vital_timing.adb
+++ b/src/vhdl/vhdl-ieee-vital_timing.adb
@@ -27,7 +27,7 @@ with Vhdl.Sem_Scopes;
with Vhdl.Sem_Specs;
with Vhdl.Evaluation;
with Vhdl.Sem;
-with Vhdl.Utils;
+with Vhdl.Utils; use Vhdl.Utils;
package body Vhdl.Ieee.Vital_Timing is
-- This package is based on IEEE 1076.4 1995.
diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb
index b74f4b307..4891f57a8 100644
--- a/src/vhdl/vhdl-nodes.adb
+++ b/src/vhdl/vhdl-nodes.adb
@@ -842,7 +842,6 @@ package body Vhdl.Nodes is
begin
Res := Create_Node (Format_Short);
Set_Nkind (Res, Iir_Kind'Pos (Iir_Kind_Error));
- Set_Base_Type (Res, Res);
return Res;
end Create_Iir_Error;
@@ -3776,21 +3775,21 @@ package body Vhdl.Nodes is
Set_Field3 (Decl, Limit);
end Set_Right_Limit_Expr;
- function Get_Base_Type (Decl : Iir) return Iir is
+ function Get_Parent_Type (Decl : Iir) return Iir is
begin
pragma Assert (Decl /= Null_Iir);
- pragma Assert (Has_Base_Type (Get_Kind (Decl)),
- "no field Base_Type");
+ pragma Assert (Has_Parent_Type (Get_Kind (Decl)),
+ "no field Parent_Type");
return Get_Field4 (Decl);
- end Get_Base_Type;
+ end Get_Parent_Type;
- procedure Set_Base_Type (Decl : Iir; Base_Type : Iir) is
+ procedure Set_Parent_Type (Decl : Iir; Base_Type : Iir) is
begin
pragma Assert (Decl /= Null_Iir);
- pragma Assert (Has_Base_Type (Get_Kind (Decl)),
- "no field Base_Type");
+ pragma Assert (Has_Parent_Type (Get_Kind (Decl)),
+ "no field Parent_Type");
Set_Field4 (Decl, Base_Type);
- end Set_Base_Type;
+ end Set_Parent_Type;
function Get_Simple_Nature (Def : Iir) return Iir is
begin
diff --git a/src/vhdl/vhdl-nodes.adb.in b/src/vhdl/vhdl-nodes.adb.in
index 913f54f7e..5c77f9fef 100644
--- a/src/vhdl/vhdl-nodes.adb.in
+++ b/src/vhdl/vhdl-nodes.adb.in
@@ -842,7 +842,6 @@ package body Vhdl.Nodes is
begin
Res := Create_Node (Format_Short);
Set_Nkind (Res, Iir_Kind'Pos (Iir_Kind_Error));
- Set_Base_Type (Res, Res);
return Res;
end Create_Iir_Error;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 629f4671e..a7ea499f3 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -2315,10 +2315,10 @@ package Vhdl.Nodes is
-- Note: a type definition cannot be anoynymous.
-- Get/Set_Type_Declarator (Field3)
--
- -- The base type.
- -- For a subtype, it returns the type.
- -- For a type, it must return the type itself.
- -- Get/Set_Base_Type (Field4)
+ -- The parent type.
+ -- This is the type or subtype which was used to build a subtype. This
+ -- creates a path to the base type. Only for subtypes.
+ -- Get/Set_Parent_Type (Field4)
--
-- The staticness of a type, according to LRM93 7.4.1.
-- Note: These types definition are always locally static:
@@ -2347,9 +2347,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Always itself
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Resolved_Flag (Flag1)
--
-- Get/Set_Signal_Type_Flag (Flag2)
@@ -2411,8 +2408,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Resolved_Flag (Flag1)
--
-- Get/Set_Signal_Type_Flag (Flag2)
@@ -2483,8 +2478,6 @@ package Vhdl.Nodes is
-- The type declarator that has created this type.
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Type staticness is always locally.
-- Get/Set_Type_Staticness (State1)
--
@@ -2521,8 +2514,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Type_Staticness (State1)
--
-- Get/Set_Constraint_State (State2)
@@ -2550,8 +2541,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Type_Staticness (State1)
--
-- Get/Set_Constraint_State (State2)
@@ -2584,8 +2573,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Next access type that also referenced the same incomplete type when
-- defined.
-- Get/Set_Incomplete_Type_Ref_Chain (Field0)
@@ -2602,8 +2589,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Resolved_Flag (Flag1)
--
-- Get/Set_Signal_Type_Flag (Flag2)
@@ -2626,8 +2611,6 @@ package Vhdl.Nodes is
-- Set to the incomplete type declaration.
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Set to the complete type definition when completed.
-- Get/Set_Complete_Type_Definition (Field5)
--
@@ -2645,8 +2628,6 @@ package Vhdl.Nodes is
-- Set to interface type declaration.
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Set only during analysis of association: type associated with this
-- interface, so that references to this interface can use the actual
-- type.
@@ -2668,8 +2649,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Attribute_Value_Chain (Field5)
--
-- Get/Set_Type_Staticness (State1)
@@ -2711,8 +2690,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Resolved_Flag (Flag1)
--
-- Get/Set_Signal_Type_Flag (Flag2)
@@ -2796,7 +2773,7 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
+ -- Get/Set_Parent_Type (Field4)
--
-- Get/Set_Resolution_Indication (Field5)
--
@@ -2818,7 +2795,7 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
+ -- Get/Set_Parent_Type (Field4)
--
-- Get/Set_Resolution_Indication (Field5)
--
@@ -2842,7 +2819,7 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
+ -- Get/Set_Parent_Type (Field4)
--
-- Get/Set_Designated_Subtype_Indication (Field5)
--
@@ -2900,7 +2877,7 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
+ -- Get/Set_Parent_Type (Field4)
--
-- Get/Set_Resolution_Indication (Field5)
--
@@ -2942,7 +2919,7 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
+ -- Get/Set_Parent_Type (Field4)
--
-- Get/Set_Type_Staticness (State1)
--
@@ -2989,7 +2966,7 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
+ -- Get/Set_Parent_Type (Field4)
--
-- Get/Set_Resolution_Indication (Field5)
--
@@ -4740,8 +4717,6 @@ package Vhdl.Nodes is
--
-- Get/Set_Type_Declarator (Field3)
--
- -- Get/Set_Base_Type (Field4)
- --
-- Get/Set_Expr_Staticness (State1)
--
-- Get/Set_Type_Staticness (Alias State1)
@@ -7987,9 +7962,9 @@ package Vhdl.Nodes is
procedure Set_Right_Limit_Expr (Decl : Iir_Range_Expression; Limit : Iir);
-- Field: Field4 Ref
- function Get_Base_Type (Decl : Iir) return Iir;
- procedure Set_Base_Type (Decl : Iir; Base_Type : Iir);
- pragma Inline (Get_Base_Type);
+ function Get_Parent_Type (Decl : Iir) return Iir;
+ procedure Set_Parent_Type (Decl : Iir; Base_Type : Iir);
+ pragma Inline (Get_Parent_Type);
-- Only for composite base nature: the simple nature.
-- Field: Field7 Ref
diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb
index 20f40cfe4..d400818a8 100644
--- a/src/vhdl/vhdl-nodes_meta.adb
+++ b/src/vhdl/vhdl-nodes_meta.adb
@@ -168,7 +168,7 @@ package body Vhdl.Nodes_Meta is
Field_Right_Limit => Type_Iir,
Field_Left_Limit_Expr => Type_Iir,
Field_Right_Limit_Expr => Type_Iir,
- Field_Base_Type => Type_Iir,
+ Field_Parent_Type => Type_Iir,
Field_Simple_Nature => Type_Iir,
Field_Base_Nature => Type_Iir,
Field_Resolution_Indication => Type_Iir,
@@ -691,8 +691,8 @@ package body Vhdl.Nodes_Meta is
return "left_limit_expr";
when Field_Right_Limit_Expr =>
return "right_limit_expr";
- when Field_Base_Type =>
- return "base_type";
+ when Field_Parent_Type =>
+ return "parent_type";
when Field_Simple_Nature =>
return "simple_nature";
when Field_Base_Nature =>
@@ -2053,7 +2053,7 @@ package body Vhdl.Nodes_Meta is
return Attr_None;
when Field_Right_Limit_Expr =>
return Attr_None;
- when Field_Base_Type =>
+ when Field_Parent_Type =>
return Attr_Ref;
when Field_Simple_Nature =>
return Attr_Ref;
@@ -2497,7 +2497,6 @@ package body Vhdl.Nodes_Meta is
Field_Type,
Field_Error_Origin,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Design_File
Field_Design_File_Directory,
Field_Design_File_Filename,
@@ -2829,7 +2828,6 @@ package body Vhdl.Nodes_Meta is
Field_Designated_Subtype_Indication,
Field_Designated_Type,
Field_Type_Declarator,
- Field_Base_Type,
Field_Incomplete_Type_Ref_Chain,
-- Iir_Kind_Incomplete_Type_Definition
Field_Resolved_Flag,
@@ -2838,7 +2836,6 @@ package body Vhdl.Nodes_Meta is
Field_Type_Staticness,
Field_Incomplete_Type_Ref_Chain,
Field_Type_Declarator,
- Field_Base_Type,
Field_Complete_Type_Definition,
-- Iir_Kind_Interface_Type_Definition
Field_Resolved_Flag,
@@ -2846,7 +2843,6 @@ package body Vhdl.Nodes_Meta is
Field_Has_Signal_Flag,
Field_Type_Staticness,
Field_Type_Declarator,
- Field_Base_Type,
Field_Associated_Type,
-- Iir_Kind_File_Type_Definition
Field_Resolved_Flag,
@@ -2855,7 +2851,6 @@ package body Vhdl.Nodes_Meta is
Field_Type_Staticness,
Field_File_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Protected_Type_Declaration
Field_Resolved_Flag,
Field_Signal_Type_Flag,
@@ -2865,7 +2860,6 @@ package body Vhdl.Nodes_Meta is
Field_Declaration_Chain,
Field_Protected_Type_Body,
Field_Type_Declarator,
- Field_Base_Type,
Field_Attribute_Value_Chain,
-- Iir_Kind_Record_Type_Definition
Field_Resolved_Flag,
@@ -2878,7 +2872,6 @@ package body Vhdl.Nodes_Meta is
Field_Constraint_State,
Field_Elements_Declaration_List,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Array_Type_Definition
Field_Resolved_Flag,
Field_Signal_Type_Flag,
@@ -2891,7 +2884,6 @@ package body Vhdl.Nodes_Meta is
Field_Index_Subtype_List,
Field_Element_Subtype,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Array_Subtype_Definition
Field_Resolved_Flag,
Field_Signal_Type_Flag,
@@ -2907,7 +2899,7 @@ package body Vhdl.Nodes_Meta is
Field_Tolerance,
Field_Element_Subtype,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
-- Iir_Kind_Record_Subtype_Definition
Field_Resolved_Flag,
Field_Is_Ref,
@@ -2919,7 +2911,7 @@ package body Vhdl.Nodes_Meta is
Field_Elements_Declaration_List,
Field_Subtype_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Resolution_Indication,
Field_Tolerance,
-- Iir_Kind_Access_Subtype_Definition
@@ -2929,7 +2921,7 @@ package body Vhdl.Nodes_Meta is
Field_Designated_Type,
Field_Subtype_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Designated_Subtype_Indication,
-- Iir_Kind_Physical_Subtype_Definition
Field_Resolved_Flag,
@@ -2940,7 +2932,7 @@ package body Vhdl.Nodes_Meta is
Field_Range_Constraint,
Field_Subtype_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Resolution_Indication,
-- Iir_Kind_Floating_Subtype_Definition
Field_Resolved_Flag,
@@ -2951,7 +2943,7 @@ package body Vhdl.Nodes_Meta is
Field_Range_Constraint,
Field_Subtype_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Resolution_Indication,
Field_Tolerance,
-- Iir_Kind_Integer_Subtype_Definition
@@ -2963,7 +2955,7 @@ package body Vhdl.Nodes_Meta is
Field_Range_Constraint,
Field_Subtype_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Resolution_Indication,
-- Iir_Kind_Enumeration_Subtype_Definition
Field_Resolved_Flag,
@@ -2974,7 +2966,7 @@ package body Vhdl.Nodes_Meta is
Field_Range_Constraint,
Field_Subtype_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Resolution_Indication,
-- Iir_Kind_Enumeration_Type_Definition
Field_Resolved_Flag,
@@ -2988,7 +2980,6 @@ package body Vhdl.Nodes_Meta is
Field_Enumeration_Literal_List,
Field_Range_Constraint,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Integer_Type_Definition
Field_Resolved_Flag,
Field_Is_Ref,
@@ -2998,7 +2989,6 @@ package body Vhdl.Nodes_Meta is
Field_Type_Staticness,
Field_Range_Constraint,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Floating_Type_Definition
Field_Resolved_Flag,
Field_Is_Ref,
@@ -3008,7 +2998,6 @@ package body Vhdl.Nodes_Meta is
Field_Type_Staticness,
Field_Range_Constraint,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Physical_Type_Definition
Field_Resolved_Flag,
Field_Is_Ref,
@@ -3021,7 +3010,6 @@ package body Vhdl.Nodes_Meta is
Field_Range_Constraint,
Field_Unit_Chain,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Range_Expression
Field_Direction,
Field_Expr_Staticness,
@@ -3045,13 +3033,12 @@ package body Vhdl.Nodes_Meta is
Field_Signal_Type_Flag,
Field_Type_Staticness,
Field_Type_Declarator,
- Field_Base_Type,
-- Iir_Kind_Subtype_Definition
Field_Is_Ref,
Field_Range_Constraint,
Field_Subtype_Type_Mark,
Field_Type_Declarator,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Resolution_Indication,
Field_Tolerance,
-- Iir_Kind_Scalar_Nature_Definition
@@ -5145,316 +5132,316 @@ package body Vhdl.Nodes_Meta is
Fields_Of_Iir_Last : constant array (Iir_Kind) of Fields_Index_Extended :=
(
Iir_Kind_Unused => -1,
- Iir_Kind_Error => 7,
- Iir_Kind_Design_File => 18,
- Iir_Kind_Design_Unit => 34,
- Iir_Kind_Library_Clause => 39,
- Iir_Kind_Use_Clause => 43,
- Iir_Kind_Context_Reference => 47,
- Iir_Kind_Integer_Literal => 52,
- Iir_Kind_Floating_Point_Literal => 57,
- Iir_Kind_Null_Literal => 59,
- Iir_Kind_String_Literal8 => 70,
- Iir_Kind_Physical_Int_Literal => 76,
- Iir_Kind_Physical_Fp_Literal => 82,
- Iir_Kind_Simple_Aggregate => 87,
- Iir_Kind_Overflow_Literal => 90,
- Iir_Kind_Unaffected_Waveform => 91,
- Iir_Kind_Waveform_Element => 94,
- Iir_Kind_Conditional_Waveform => 98,
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+ Iir_Kind_Concurrent_Selected_Signal_Assignment => 1573,
+ Iir_Kind_Concurrent_Assertion_Statement => 1581,
+ Iir_Kind_Concurrent_Procedure_Call_Statement => 1588,
+ Iir_Kind_Concurrent_Break_Statement => 1596,
+ Iir_Kind_Psl_Assert_Directive => 1609,
+ Iir_Kind_Psl_Assume_Directive => 1620,
+ Iir_Kind_Psl_Cover_Directive => 1632,
+ Iir_Kind_Psl_Restrict_Directive => 1643,
+ Iir_Kind_Block_Statement => 1657,
+ Iir_Kind_If_Generate_Statement => 1668,
+ Iir_Kind_Case_Generate_Statement => 1677,
+ Iir_Kind_For_Generate_Statement => 1686,
+ Iir_Kind_Component_Instantiation_Statement => 1697,
+ Iir_Kind_Psl_Default_Clock => 1701,
+ Iir_Kind_Generate_Statement_Body => 1712,
+ Iir_Kind_If_Generate_Else_Clause => 1718,
+ Iir_Kind_Simple_Simultaneous_Statement => 1725,
+ Iir_Kind_Simultaneous_Null_Statement => 1729,
+ Iir_Kind_Simultaneous_Procedural_Statement => 1740,
+ Iir_Kind_Simultaneous_Case_Statement => 1749,
+ Iir_Kind_Simultaneous_If_Statement => 1758,
+ Iir_Kind_Simultaneous_Elsif => 1764,
+ Iir_Kind_Simple_Signal_Assignment_Statement => 1775,
+ Iir_Kind_Conditional_Signal_Assignment_Statement => 1786,
+ Iir_Kind_Selected_Waveform_Assignment_Statement => 1798,
+ Iir_Kind_Null_Statement => 1802,
+ Iir_Kind_Assertion_Statement => 1809,
+ Iir_Kind_Report_Statement => 1815,
+ Iir_Kind_Wait_Statement => 1823,
+ Iir_Kind_Variable_Assignment_Statement => 1830,
+ Iir_Kind_Conditional_Variable_Assignment_Statement => 1837,
+ Iir_Kind_Return_Statement => 1843,
+ Iir_Kind_For_Loop_Statement => 1854,
+ Iir_Kind_While_Loop_Statement => 1865,
+ Iir_Kind_Next_Statement => 1872,
+ Iir_Kind_Exit_Statement => 1879,
+ Iir_Kind_Case_Statement => 1887,
+ Iir_Kind_Procedure_Call_Statement => 1893,
+ Iir_Kind_Break_Statement => 1900,
+ Iir_Kind_If_Statement => 1910,
+ Iir_Kind_Elsif => 1916,
+ Iir_Kind_Character_Literal => 1924,
+ Iir_Kind_Simple_Name => 1932,
+ Iir_Kind_Selected_Name => 1941,
+ Iir_Kind_Operator_Symbol => 1947,
+ Iir_Kind_Reference_Name => 1952,
+ Iir_Kind_External_Constant_Name => 1961,
+ Iir_Kind_External_Signal_Name => 1970,
+ Iir_Kind_External_Variable_Name => 1980,
+ Iir_Kind_Selected_By_All_Name => 1986,
+ Iir_Kind_Parenthesis_Name => 1991,
+ Iir_Kind_Package_Pathname => 1995,
+ Iir_Kind_Absolute_Pathname => 1996,
+ Iir_Kind_Relative_Pathname => 1997,
+ Iir_Kind_Pathname_Element => 2002,
+ Iir_Kind_Base_Attribute => 2004,
+ Iir_Kind_Subtype_Attribute => 2009,
+ Iir_Kind_Element_Attribute => 2014,
+ Iir_Kind_Across_Attribute => 2019,
+ Iir_Kind_Through_Attribute => 2024,
+ Iir_Kind_Nature_Reference_Attribute => 2028,
+ Iir_Kind_Left_Type_Attribute => 2033,
+ Iir_Kind_Right_Type_Attribute => 2038,
+ Iir_Kind_High_Type_Attribute => 2043,
+ Iir_Kind_Low_Type_Attribute => 2048,
+ Iir_Kind_Ascending_Type_Attribute => 2053,
+ Iir_Kind_Image_Attribute => 2059,
+ Iir_Kind_Value_Attribute => 2065,
+ Iir_Kind_Pos_Attribute => 2071,
+ Iir_Kind_Val_Attribute => 2077,
+ Iir_Kind_Succ_Attribute => 2083,
+ Iir_Kind_Pred_Attribute => 2089,
+ Iir_Kind_Leftof_Attribute => 2095,
+ Iir_Kind_Rightof_Attribute => 2101,
+ Iir_Kind_Signal_Slew_Attribute => 2109,
+ Iir_Kind_Quantity_Slew_Attribute => 2117,
+ Iir_Kind_Ramp_Attribute => 2125,
+ Iir_Kind_Zoh_Attribute => 2133,
+ Iir_Kind_Ltf_Attribute => 2141,
+ Iir_Kind_Ztf_Attribute => 2151,
+ Iir_Kind_Dot_Attribute => 2158,
+ Iir_Kind_Integ_Attribute => 2165,
+ Iir_Kind_Above_Attribute => 2173,
+ Iir_Kind_Quantity_Delayed_Attribute => 2181,
+ Iir_Kind_Delayed_Attribute => 2190,
+ Iir_Kind_Stable_Attribute => 2199,
+ Iir_Kind_Quiet_Attribute => 2208,
+ Iir_Kind_Transaction_Attribute => 2217,
+ Iir_Kind_Event_Attribute => 2221,
+ Iir_Kind_Active_Attribute => 2225,
+ Iir_Kind_Last_Event_Attribute => 2229,
+ Iir_Kind_Last_Active_Attribute => 2233,
+ Iir_Kind_Last_Value_Attribute => 2237,
+ Iir_Kind_Driving_Attribute => 2241,
+ Iir_Kind_Driving_Value_Attribute => 2245,
+ Iir_Kind_Behavior_Attribute => 2245,
+ Iir_Kind_Structure_Attribute => 2245,
+ Iir_Kind_Simple_Name_Attribute => 2252,
+ Iir_Kind_Instance_Name_Attribute => 2257,
+ Iir_Kind_Path_Name_Attribute => 2262,
+ Iir_Kind_Left_Array_Attribute => 2269,
+ Iir_Kind_Right_Array_Attribute => 2276,
+ Iir_Kind_High_Array_Attribute => 2283,
+ Iir_Kind_Low_Array_Attribute => 2290,
+ Iir_Kind_Length_Array_Attribute => 2297,
+ Iir_Kind_Ascending_Array_Attribute => 2304,
+ Iir_Kind_Range_Array_Attribute => 2311,
+ Iir_Kind_Reverse_Range_Array_Attribute => 2318,
+ Iir_Kind_Attribute_Name => 2327
);
function Get_Fields_First (K : Iir_Kind) return Fields_Index is
@@ -6077,8 +6064,8 @@ package body Vhdl.Nodes_Meta is
return Get_Left_Limit_Expr (N);
when Field_Right_Limit_Expr =>
return Get_Right_Limit_Expr (N);
- when Field_Base_Type =>
- return Get_Base_Type (N);
+ when Field_Parent_Type =>
+ return Get_Parent_Type (N);
when Field_Simple_Nature =>
return Get_Simple_Nature (N);
when Field_Base_Nature =>
@@ -6533,8 +6520,8 @@ package body Vhdl.Nodes_Meta is
Set_Left_Limit_Expr (N, V);
when Field_Right_Limit_Expr =>
Set_Right_Limit_Expr (N, V);
- when Field_Base_Type =>
- Set_Base_Type (N, V);
+ when Field_Parent_Type =>
+ Set_Parent_Type (N, V);
when Field_Simple_Nature =>
Set_Simple_Nature (N, V);
when Field_Base_Nature =>
@@ -9491,35 +9478,22 @@ package body Vhdl.Nodes_Meta is
return K = Iir_Kind_Range_Expression;
end Has_Right_Limit_Expr;
- function Has_Base_Type (K : Iir_Kind) return Boolean is
+ function Has_Parent_Type (K : Iir_Kind) return Boolean is
begin
case K is
- when Iir_Kind_Error
- | Iir_Kind_Access_Type_Definition
- | Iir_Kind_Incomplete_Type_Definition
- | Iir_Kind_Interface_Type_Definition
- | Iir_Kind_File_Type_Definition
- | Iir_Kind_Protected_Type_Declaration
- | Iir_Kind_Record_Type_Definition
- | Iir_Kind_Array_Type_Definition
- | Iir_Kind_Array_Subtype_Definition
+ when Iir_Kind_Array_Subtype_Definition
| Iir_Kind_Record_Subtype_Definition
| Iir_Kind_Access_Subtype_Definition
| Iir_Kind_Physical_Subtype_Definition
| Iir_Kind_Floating_Subtype_Definition
| Iir_Kind_Integer_Subtype_Definition
| Iir_Kind_Enumeration_Subtype_Definition
- | Iir_Kind_Enumeration_Type_Definition
- | Iir_Kind_Integer_Type_Definition
- | Iir_Kind_Floating_Type_Definition
- | Iir_Kind_Physical_Type_Definition
- | Iir_Kind_Wildcard_Type_Definition
| Iir_Kind_Subtype_Definition =>
return True;
when others =>
return False;
end case;
- end Has_Base_Type;
+ end Has_Parent_Type;
function Has_Simple_Nature (K : Iir_Kind) return Boolean is
begin
diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads
index 80fe7d136..1b5a19269 100644
--- a/src/vhdl/vhdl-nodes_meta.ads
+++ b/src/vhdl/vhdl-nodes_meta.ads
@@ -211,7 +211,7 @@ package Vhdl.Nodes_Meta is
Field_Right_Limit,
Field_Left_Limit_Expr,
Field_Right_Limit_Expr,
- Field_Base_Type,
+ Field_Parent_Type,
Field_Simple_Nature,
Field_Base_Nature,
Field_Resolution_Indication,
@@ -783,7 +783,7 @@ package Vhdl.Nodes_Meta is
function Has_Right_Limit (K : Iir_Kind) return Boolean;
function Has_Left_Limit_Expr (K : Iir_Kind) return Boolean;
function Has_Right_Limit_Expr (K : Iir_Kind) return Boolean;
- function Has_Base_Type (K : Iir_Kind) return Boolean;
+ function Has_Parent_Type (K : Iir_Kind) return Boolean;
function Has_Simple_Nature (K : Iir_Kind) return Boolean;
function Has_Base_Nature (K : Iir_Kind) return Boolean;
function Has_Resolution_Indication (K : Iir_Kind) return Boolean;
diff --git a/src/vhdl/vhdl-sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb
index 927877458..67e9699d9 100644
--- a/src/vhdl/vhdl-sem_assocs.adb
+++ b/src/vhdl/vhdl-sem_assocs.adb
@@ -955,7 +955,7 @@ package body Vhdl.Sem_Assocs is
Error_Kind ("finish_individual_assoc_array", Base_Index);
end case;
Location_Copy (Actual_Index, Actual);
- Set_Base_Type (Actual_Index, Get_Base_Type (Base_Index));
+ Set_Parent_Type (Actual_Index, Base_Index);
Index_Constraint := Get_Range_Constraint (Base_Index);
Index_Subtype_Constraint := Create_Iir (Iir_Kind_Range_Expression);
@@ -1070,7 +1070,7 @@ package body Vhdl.Sem_Assocs is
Ntype := Create_Iir (Iir_Kind_Record_Subtype_Definition);
Set_Is_Ref (Ntype, True);
Location_Copy (Ntype, Assoc);
- Set_Base_Type (Ntype, Get_Base_Type (Atype));
+ Set_Parent_Type (Ntype, Atype);
if Get_Kind (Atype) = Iir_Kind_Record_Subtype_Definition then
Set_Resolution_Indication
(Ntype, Get_Resolution_Indication (Atype));
diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb
index d85a0631a..8b365a225 100644
--- a/src/vhdl/vhdl-sem_decls.adb
+++ b/src/vhdl/vhdl-sem_decls.adb
@@ -552,7 +552,6 @@ package body Vhdl.Sem_Decls is
Set_Location (Def, Get_Location (Inter));
Set_Type_Declarator (Def, Inter);
Set_Type (Inter, Def);
- Set_Base_Type (Def, Def);
Set_Type_Staticness (Def, None);
Set_Resolved_Flag (Def, False);
Set_Signal_Type_Flag (Def, True);
@@ -704,7 +703,6 @@ package body Vhdl.Sem_Decls is
Def := Create_Iir (Iir_Kind_Incomplete_Type_Definition);
Location_Copy (Def, Decl);
Set_Type_Definition (Decl, Def);
- Set_Base_Type (Def, Def);
Set_Signal_Type_Flag (Def, True);
Set_Type_Declarator (Def, Decl);
Set_Visible_Flag (Decl, True);
diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb
index 49ad9ed8a..07da48d8d 100644
--- a/src/vhdl/vhdl-sem_expr.adb
+++ b/src/vhdl/vhdl-sem_expr.adb
@@ -3775,7 +3775,7 @@ package body Vhdl.Sem_Expr is
Error_Kind ("sem_array_aggregate(2)", Index_Type);
end case;
Location_Copy (Info.Index_Subtype, Aggr);
- Set_Base_Type (Info.Index_Subtype, Get_Base_Type (Index_Type));
+ Set_Parent_Type (Info.Index_Subtype, Get_Base_Type (Index_Type));
Index_Constraint := Get_Range_Constraint (Index_Type);
-- LRM93 7.3.2.2
@@ -4913,7 +4913,6 @@ package body Vhdl.Sem_Expr is
-- Always ok.
-- Use the error as a type.
Set_Type (Expr, Expr);
- Set_Base_Type (Expr, Expr);
return Expr;
when others =>
diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb
index 107bb46cb..11333e1fd 100644
--- a/src/vhdl/vhdl-sem_names.adb
+++ b/src/vhdl/vhdl-sem_names.adb
@@ -825,7 +825,7 @@ package body Vhdl.Sem_Names is
Set_Range_Constraint (Slice_Type, Suffix_Rng);
Set_Is_Ref (Slice_Type, True);
Set_Type_Staticness (Slice_Type, Staticness);
- Set_Base_Type (Slice_Type, Get_Base_Type (Index_Type));
+ Set_Parent_Type (Slice_Type, Get_Base_Type (Index_Type));
Set_Location (Slice_Type, Get_Location (Suffix));
-- Attach the new index subtype to the array subtype.
@@ -838,7 +838,7 @@ package body Vhdl.Sem_Names is
Set_Index_Subtype_List (Expr_Type, Index_List);
Set_Nth_Element (Index_List, 0, Slice_Type);
Prefix_Base_Type := Get_Base_Type (Prefix_Type);
- Set_Base_Type (Expr_Type, Prefix_Base_Type);
+ Set_Parent_Type (Expr_Type, Prefix_Base_Type);
Set_Signal_Type_Flag (Expr_Type,
Get_Signal_Type_Flag (Prefix_Base_Type));
Set_Element_Subtype (Expr_Type, Get_Element_Subtype (Prefix_Type));
diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb
index 759e0af3f..10c84d41c 100644
--- a/src/vhdl/vhdl-sem_types.adb
+++ b/src/vhdl/vhdl-sem_types.adb
@@ -247,11 +247,10 @@ package body Vhdl.Sem_Types is
Location_Copy (Ntype, Loc);
Ndef := Create_Iir (Iir_Kind_Integer_Type_Definition);
Location_Copy (Ndef, Loc);
- Set_Base_Type (Ndef, Ndef);
Set_Type_Declarator (Ndef, Decl);
Set_Type_Staticness (Ndef, Locally);
Set_Signal_Type_Flag (Ndef, True);
- Set_Base_Type (Ntype, Ndef);
+ Set_Parent_Type (Ntype, Ndef);
Set_Type_Declarator (Ntype, Decl);
Set_Range_Constraint (Ntype, Constraint);
Set_Type_Staticness (Ntype, Get_Expr_Staticness (Constraint));
@@ -302,12 +301,11 @@ package body Vhdl.Sem_Types is
Location_Copy (Ntype, Expr);
Ndef := Create_Iir (Iir_Kind_Floating_Type_Definition);
Location_Copy (Ndef, Expr);
- Set_Base_Type (Ndef, Ndef);
Set_Type_Declarator (Ndef, Decl);
Set_Type_Staticness (Ndef, Get_Expr_Staticness (Expr));
Set_Scalar_Size (Ndef, Scalar_64);
Set_Signal_Type_Flag (Ndef, True);
- Set_Base_Type (Ntype, Ndef);
+ Set_Parent_Type (Ntype, Ndef);
Set_Type_Declarator (Ntype, Decl);
Set_Range_Constraint (Ntype, Rng);
Set_Resolved_Flag (Ntype, False);
@@ -369,7 +367,6 @@ package body Vhdl.Sem_Types is
-- type and a subtype of the base type, in which case the simple name
-- denotes the subtype, and the base type is anonymous.
Set_Type_Declarator (Def, Decl);
- Set_Base_Type (Def, Def);
Set_Resolved_Flag (Def, False);
Set_Type_Staticness (Def, Locally);
Set_Signal_Type_Flag (Def, True);
@@ -414,7 +411,7 @@ package body Vhdl.Sem_Types is
-- Create the subtype.
Sub_Type := Create_Iir (Iir_Kind_Physical_Subtype_Definition);
Location_Copy (Sub_Type, Range_Expr);
- Set_Base_Type (Sub_Type, Def);
+ Set_Parent_Type (Sub_Type, Def);
Set_Signal_Type_Flag (Sub_Type, True);
-- Analyze the primary unit.
@@ -579,7 +576,6 @@ package body Vhdl.Sem_Types is
El : Iir;
begin
Decl := Get_Type_Definition (Type_Decl);
- Set_Base_Type (Decl, Decl);
Set_Resolved_Flag (Decl, False);
Set_Signal_Type_Flag (Decl, False);
Set_Type_Staticness (Decl, None);
@@ -822,7 +818,6 @@ package body Vhdl.Sem_Types is
El: Iir;
Only_Characters : Boolean;
begin
- Set_Base_Type (Def, Def);
Set_Type_Staticness (Def, Locally);
Set_Signal_Type_Flag (Def, True);
@@ -939,7 +934,6 @@ package body Vhdl.Sem_Types is
Xref_Decl (El);
end loop;
Close_Declarative_Region;
- Set_Base_Type (Def, Def);
Set_Resolved_Flag (Def, Resolved_Flag);
Set_Type_Staticness (Def, Type_Staticness);
Set_Constraint_State (Def, Constraint);
@@ -973,8 +967,6 @@ package body Vhdl.Sem_Types is
function Sem_Unbounded_Array_Type_Definition (Def: Iir) return Iir is
begin
- Set_Base_Type (Def, Def);
-
Sem_Unbounded_Array_Indexes (Def);
Sem_Array_Element (Def);
@@ -1044,7 +1036,6 @@ package body Vhdl.Sem_Types is
-- Create a definition for the base type of subtype DEF.
Base_Type := Create_Iir (Iir_Kind_Array_Type_Definition);
Location_Copy (Base_Type, Def);
- Set_Base_Type (Base_Type, Base_Type);
Set_Type_Declarator (Base_Type, Decl);
Base_Index_List := Create_Iir_Flist (Get_Nbr_Elements (Index_List));
Set_Index_Subtype_Definition_List (Base_Type, Base_Index_List);
@@ -1116,7 +1107,7 @@ package body Vhdl.Sem_Types is
Set_Index_Constraint_Flag (Def, True);
Set_Constraint_State (Def, Get_Array_Constraint (Def));
Set_Constraint_State (Base_Type, Get_Array_Constraint (Base_Type));
- Set_Base_Type (Def, Base_Type);
+ Set_Parent_Type (Def, Base_Type);
Set_Subtype_Type_Mark (Def, Null_Iir);
return Def;
end Sem_Constrained_Array_Type_Definition;
@@ -1151,7 +1142,6 @@ package body Vhdl.Sem_Types is
end case;
Set_Designated_Type (Def, D_Type);
end if;
- Set_Base_Type (Def, Def);
Set_Type_Staticness (Def, None);
Set_Resolved_Flag (Def, False);
Set_Signal_Type_Flag (Def, False);
@@ -1210,7 +1200,6 @@ package body Vhdl.Sem_Types is
end case;
end if;
- Set_Base_Type (Def, Def);
Set_Resolved_Flag (Def, False);
Set_Text_File_Flag (Def, Is_Text_Type_Declaration (Decl));
Set_Signal_Type_Flag (Def, False);
@@ -1311,7 +1300,7 @@ package body Vhdl.Sem_Types is
end case;
Location_Copy (Sub_Type, A_Range);
Set_Range_Constraint (Sub_Type, A_Range);
- Set_Base_Type (Sub_Type, Get_Base_Type (Range_Type));
+ Set_Parent_Type (Sub_Type, Get_Base_Type (Range_Type));
Set_Type_Staticness (Sub_Type, Get_Expr_Staticness (A_Range));
Set_Signal_Type_Flag (Sub_Type, True);
return Sub_Type;
@@ -1539,7 +1528,7 @@ package body Vhdl.Sem_Types is
Error_Kind ("copy_subtype_indication", Def);
end case;
Location_Copy (Res, Def);
- Set_Base_Type (Res, Get_Base_Type (Def));
+ Set_Parent_Type (Res, Get_Base_Type (Def));
Set_Type_Staticness (Res, Get_Type_Staticness (Def));
Set_Signal_Type_Flag (Res, Get_Signal_Type_Flag (Def));
return Res;
@@ -1577,7 +1566,7 @@ package body Vhdl.Sem_Types is
Location_Copy (Res, Loc);
-- FIXME: can be globally!
Set_Type_Staticness (Res, None);
- Set_Base_Type (Res, Get_Base_Type (Atype));
+ Set_Parent_Type (Res, Get_Base_Type (Atype));
Set_Signal_Type_Flag (Res, Get_Signal_Type_Flag (Atype));
Set_Resolved_Flag (Res, Get_Resolved_Flag (Atype));
Set_Constraint_State (Res, Fully_Constrained);
@@ -1700,7 +1689,7 @@ package body Vhdl.Sem_Types is
Index_Staticness : Iir_Staticness;
begin
-- Check each index constraint against array type.
- Set_Base_Type (Def, Base_Type);
+ Set_Parent_Type (Def, Base_Type);
Sem_Array_Constraint_Indexes
(Def, Type_Mark, Base_Type, Index_Staticness);
@@ -1980,7 +1969,7 @@ package body Vhdl.Sem_Types is
Res := Create_Iir (Iir_Kind_Record_Subtype_Definition);
Set_Is_Ref (Res, True);
Location_Copy (Res, Def);
- Set_Base_Type (Res, Get_Base_Type (Type_Mark));
+ Set_Parent_Type (Res, Type_Mark);
if Get_Kind (Type_Mark) = Iir_Kind_Record_Subtype_Definition then
Set_Resolution_Indication
(Res, Get_Resolution_Indication (Type_Mark));
@@ -2222,7 +2211,7 @@ package body Vhdl.Sem_Types is
Res := Create_Iir (Get_Kind (Type_Mark));
end if;
Location_Copy (Res, Def);
- Set_Base_Type (Res, Get_Base_Type (Type_Mark));
+ Set_Parent_Type (Res, Type_Mark);
Set_Resolution_Indication (Res, Get_Resolution_Indication (Def));
A_Range := Get_Range_Constraint (Def);
if A_Range = Null_Iir then
@@ -2324,7 +2313,7 @@ package body Vhdl.Sem_Types is
(Def, Base_Type, Null_Iir);
Res := Create_Iir (Iir_Kind_Access_Subtype_Definition);
Location_Copy (Res, Def);
- Set_Base_Type (Res, Type_Mark);
+ Set_Parent_Type (Res, Type_Mark);
Set_Designated_Subtype_Indication (Res, Sub_Type);
Set_Signal_Type_Flag (Res, False);
@@ -2409,7 +2398,6 @@ package body Vhdl.Sem_Types is
Type_Mark := Sem_Type_Mark (Def, Incomplete);
return Type_Mark;
when Iir_Kind_Error =>
- Set_Base_Type (Def, Def);
return Def;
when others =>
null;
@@ -2529,7 +2517,7 @@ package body Vhdl.Sem_Types is
Location_Copy (St_Def, Def);
Set_Index_Subtype_List (St_Def, Get_Index_Subtype_List (Def));
Set_Element_Subtype (St_Def, Get_Element_Subtype (Br_Def));
- Set_Base_Type (St_Def, Get_Base_Type (Br_Def));
+ Set_Parent_Type (St_Def, Br_Def);
Set_Type_Staticness (St_Def, Get_Nature_Staticness (Def));
Set_Constraint_State (St_Def, Get_Constraint_State (Def));
Set_Type_Declarator (St_Def, Get_Nature_Declarator (Def));
@@ -2636,7 +2624,6 @@ package body Vhdl.Sem_Types is
Arr := Create_Iir (Iir_Kind_Array_Type_Definition);
Location_Copy (Arr, Def);
Set_Index_Subtype_List (Arr, Get_Index_Subtype_List (Def));
- Set_Base_Type (Arr, Arr);
Set_Type_Staticness (Arr, None);
Set_Type_Declarator (Arr, Decl);
Set_Element_Subtype (Arr, Get_Branch_Type (El_Nat, I));
@@ -2748,7 +2735,6 @@ package body Vhdl.Sem_Types is
St_Def := Create_Iir (Iir_Kind_Record_Type_Definition);
Location_Copy (St_Def, Def);
Set_Type_Declarator (St_Def, Decl);
- Set_Base_Type (St_Def, St_Def);
St_List := Create_Iir_Flist (Get_Nbr_Elements (El_List));
Set_Elements_Declaration_List (St_Def, St_List);
Staticness := Locally;
diff --git a/src/vhdl/vhdl-std_package.adb b/src/vhdl/vhdl-std_package.adb
index c9d1ce938..5fa8fc2fd 100644
--- a/src/vhdl/vhdl-std_package.adb
+++ b/src/vhdl/vhdl-std_package.adb
@@ -261,7 +261,6 @@ package body Vhdl.Std_Package is
begin
--Integer_Type_Definition :=
-- Create_Std_Iir (Iir_Kind_Integer_Type_Definition);
- Set_Base_Type (Type_Definition, Type_Definition);
Set_Type_Staticness (Type_Definition, Locally);
Set_Signal_Type_Flag (Type_Definition, True);
Set_Has_Signal_Flag (Type_Definition, not Flags.Flag_Whole_Analyze);
@@ -282,7 +281,7 @@ package body Vhdl.Std_Package is
begin
Subtype_Definition :=
Create_Std_Iir (Iir_Kind_Integer_Subtype_Definition);
- Set_Base_Type (Subtype_Definition, Type_Definition);
+ Set_Parent_Type (Subtype_Definition, Type_Definition);
Constraint := Create_Std_Range_Expr
(Create_Std_Integer (Low_Bound (Is_64),
Universal_Integer_Type_Definition),
@@ -316,7 +315,6 @@ package body Vhdl.Std_Package is
Index := Create_Std_Type_Mark (Natural_Subtype_Declaration);
Def := Create_Std_Iir (Iir_Kind_Array_Type_Definition);
- Set_Base_Type (Def, Def);
Index_List := Create_Iir_Flist (1);
Set_Index_Subtype_Definition_List (Def, Index_List);
@@ -403,7 +401,6 @@ package body Vhdl.Std_Package is
begin
Decl := Create_Std_Decl (Iir_Kind_Type_Declaration);
Set_Identifier (Decl, Name_Table.Get_Identifier (Name));
- Set_Base_Type (Def, Def);
Set_Type_Staticness (Def, None);
Set_Type_Definition (Decl, Def);
Set_Type_Declarator (Def, Decl);
@@ -462,7 +459,6 @@ package body Vhdl.Std_Package is
-- (false, true)
Boolean_Type_Definition :=
Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition);
- Set_Base_Type (Boolean_Type_Definition, Boolean_Type_Definition);
Set_Enumeration_Literal_List
(Boolean_Type_Definition, Create_Iir_Flist (2));
Boolean_False := Create_Std_Literal
@@ -501,7 +497,6 @@ package body Vhdl.Std_Package is
Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition);
Set_Enumeration_Literal_List
(Bit_Type_Definition, Create_Iir_Flist (2));
- Set_Base_Type (Bit_Type_Definition, Bit_Type_Definition);
Set_Is_Character_Type (Bit_Type_Definition, True);
Bit_0 := Create_Std_Literal
(Get_Std_Character ('0'), 0, Bit_Type_Definition);
@@ -540,7 +535,6 @@ package body Vhdl.Std_Package is
begin
Character_Type_Definition :=
Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition);
- Set_Base_Type (Character_Type_Definition, Character_Type_Definition);
Set_Is_Character_Type (Character_Type_Definition, True);
if Vhdl_Std = Vhdl_87 then
Len := 128;
@@ -592,8 +586,6 @@ package body Vhdl.Std_Package is
-- (note, warning, error, failure)
Severity_Level_Type_Definition :=
Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition);
- Set_Base_Type (Severity_Level_Type_Definition,
- Severity_Level_Type_Definition);
Set_Enumeration_Literal_List
(Severity_Level_Type_Definition, Create_Iir_Flist (4));
Set_Scalar_Size (Severity_Level_Type_Definition, Scalar_8);
@@ -652,8 +644,6 @@ package body Vhdl.Std_Package is
declare
Constraint : Iir_Range_Expression;
begin
- Set_Base_Type (Universal_Real_Type_Definition,
- Universal_Real_Type_Definition);
Set_Type_Staticness (Universal_Real_Type_Definition, Locally);
Set_Signal_Type_Flag (Universal_Real_Type_Definition, True);
Set_Has_Signal_Flag (Universal_Real_Type_Definition, False);
@@ -670,8 +660,8 @@ package body Vhdl.Std_Package is
Universal_Real_Subtype_Definition :=
Create_Std_Iir (Iir_Kind_Floating_Subtype_Definition);
- Set_Base_Type (Universal_Real_Subtype_Definition,
- Universal_Real_Type_Definition);
+ Set_Parent_Type (Universal_Real_Subtype_Definition,
+ Universal_Real_Type_Definition);
Constraint := Create_Std_Range_Expr
(Create_Std_Fp (Fp64'First, Universal_Real_Type_Definition),
Create_Std_Fp (Fp64'Last, Universal_Real_Type_Definition),
@@ -718,8 +708,6 @@ package body Vhdl.Std_Package is
end;
begin
- Set_Base_Type (Convertible_Real_Type_Definition,
- Convertible_Real_Type_Definition);
Set_Type_Staticness (Convertible_Real_Type_Definition, Locally);
Set_Signal_Type_Flag (Convertible_Real_Type_Definition, True);
Set_Has_Signal_Flag (Convertible_Real_Type_Definition, False);
@@ -772,7 +760,6 @@ package body Vhdl.Std_Package is
begin
Real_Type_Definition :=
Create_Std_Iir (Iir_Kind_Floating_Type_Definition);
- Set_Base_Type (Real_Type_Definition, Real_Type_Definition);
Set_Type_Staticness (Real_Type_Definition, Locally);
Set_Signal_Type_Flag (Real_Type_Definition, True);
Set_Has_Signal_Flag (Real_Type_Definition,
@@ -790,7 +777,7 @@ package body Vhdl.Std_Package is
Real_Subtype_Definition :=
Create_Std_Iir (Iir_Kind_Floating_Subtype_Definition);
- Set_Base_Type (Real_Subtype_Definition, Real_Type_Definition);
+ Set_Parent_Type (Real_Subtype_Definition, Real_Type_Definition);
Constraint := Create_Std_Range_Expr
(Create_Std_Fp (Fp64'First, Universal_Real_Type_Definition),
Create_Std_Fp (Fp64'Last, Universal_Real_Type_Definition),
@@ -878,7 +865,6 @@ package body Vhdl.Std_Package is
Time_Type_Definition :=
Create_Std_Iir (Iir_Kind_Physical_Type_Definition);
- Set_Base_Type (Time_Type_Definition, Time_Type_Definition);
Set_Type_Staticness (Time_Type_Definition, Locally);--Time_Staticness
Set_Signal_Type_Flag (Time_Type_Definition, True);
Set_Has_Signal_Flag (Time_Type_Definition,
@@ -932,7 +918,7 @@ package body Vhdl.Std_Package is
Time_Fs_Unit),
Time_Type_Definition);
Set_Range_Constraint (Time_Subtype_Definition, Constraint);
- Set_Base_Type (Time_Subtype_Definition, Time_Type_Definition);
+ Set_Parent_Type (Time_Subtype_Definition, Time_Type_Definition);
--Set_Subtype_Type_Mark (Time_Subtype_Definition,
-- Time_Type_Definition);
Set_Type_Staticness (Time_Subtype_Definition, Time_Staticness);
@@ -967,7 +953,7 @@ package body Vhdl.Std_Package is
Time_Fs_Unit),
Time_Type_Definition);
Set_Range_Constraint (Delay_Length_Subtype_Definition, Constraint);
- Set_Base_Type
+ Set_Parent_Type
(Delay_Length_Subtype_Definition, Time_Type_Definition);
Set_Type_Staticness
(Delay_Length_Subtype_Definition, Time_Staticness);
@@ -999,8 +985,6 @@ package body Vhdl.Std_Package is
if AMS_Vhdl then
Domain_Type_Type_Definition :=
Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition);
- Set_Base_Type (Domain_Type_Type_Definition,
- Domain_Type_Type_Definition);
Set_Enumeration_Literal_List
(Domain_Type_Type_Definition, Create_Iir_Flist (3));
Set_Scalar_Size (Domain_Type_Type_Definition, Scalar_8);
@@ -1119,7 +1103,7 @@ package body Vhdl.Std_Package is
begin
Natural_Subtype_Definition :=
Create_Std_Iir (Iir_Kind_Integer_Subtype_Definition);
- Set_Base_Type (Natural_Subtype_Definition, Integer_Type_Definition);
+ Set_Parent_Type (Natural_Subtype_Definition, Integer_Type_Definition);
Set_Subtype_Type_Mark
(Natural_Subtype_Definition,
Create_Std_Type_Mark (Integer_Subtype_Declaration));
@@ -1151,8 +1135,8 @@ package body Vhdl.Std_Package is
begin
Positive_Subtype_Definition :=
Create_Std_Iir (Iir_Kind_Integer_Subtype_Definition);
- Set_Base_Type (Positive_Subtype_Definition,
- Integer_Type_Definition);
+ Set_Parent_Type (Positive_Subtype_Definition,
+ Integer_Type_Definition);
Set_Subtype_Type_Mark
(Positive_Subtype_Definition,
Create_Std_Type_Mark (Integer_Subtype_Declaration));
@@ -1188,7 +1172,6 @@ package body Vhdl.Std_Package is
String_Type_Definition :=
Create_Std_Iir (Iir_Kind_Array_Type_Definition);
- Set_Base_Type (String_Type_Definition, String_Type_Definition);
Index_List := Create_Iir_Flist (1);
Set_Nth_Element (Index_List, 0,
Create_Std_Type_Mark (Positive_Subtype_Declaration));
@@ -1263,8 +1246,6 @@ package body Vhdl.Std_Package is
if Vhdl_Std >= Vhdl_93 then
File_Open_Kind_Type_Definition :=
Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition);
- Set_Base_Type (File_Open_Kind_Type_Definition,
- File_Open_Kind_Type_Definition);
Set_Enumeration_Literal_List
(File_Open_Kind_Type_Definition, Create_Iir_Flist (3));
Set_Scalar_Size (File_Open_Kind_Type_Definition, Scalar_8);
@@ -1302,8 +1283,6 @@ package body Vhdl.Std_Package is
if Vhdl_Std >= Vhdl_93 then
File_Open_Status_Type_Definition :=
Create_Std_Iir (Iir_Kind_Enumeration_Type_Definition);
- Set_Base_Type (File_Open_Status_Type_Definition,
- File_Open_Status_Type_Definition);
Set_Enumeration_Literal_List
(File_Open_Status_Type_Definition, Create_Iir_Flist (4));
Set_Scalar_Size (File_Open_Status_Type_Definition, Scalar_8);
diff --git a/src/vhdl/vhdl-utils.adb b/src/vhdl/vhdl-utils.adb
index 116d3dcb1..030889fc5 100644
--- a/src/vhdl/vhdl-utils.adb
+++ b/src/vhdl/vhdl-utils.adb
@@ -992,6 +992,41 @@ package body Vhdl.Utils is
end if;
end Clear_Seen_Flag;
+ function Get_Base_Type (Atype : Iir) return Iir
+ is
+ Res : Iir;
+ begin
+ Res := Atype;
+ loop
+ case Get_Kind (Res) is
+ when Iir_Kind_Access_Type_Definition
+ | Iir_Kind_Integer_Type_Definition
+ | Iir_Kind_Floating_Type_Definition
+ | Iir_Kind_Enumeration_Type_Definition
+ | Iir_Kind_Physical_Type_Definition
+ | Iir_Kind_Array_Type_Definition
+ | Iir_Kind_Record_Type_Definition
+ | Iir_Kind_Protected_Type_Declaration
+ | Iir_Kind_File_Type_Definition
+ | Iir_Kind_Incomplete_Type_Definition
+ | Iir_Kind_Interface_Type_Definition
+ | Iir_Kind_Wildcard_Type_Definition
+ | Iir_Kind_Error =>
+ return Res;
+ when Iir_Kind_Access_Subtype_Definition
+ | Iir_Kind_Integer_Subtype_Definition
+ | Iir_Kind_Floating_Subtype_Definition
+ | Iir_Kind_Enumeration_Subtype_Definition
+ | Iir_Kind_Physical_Subtype_Definition
+ | Iir_Kind_Array_Subtype_Definition
+ | Iir_Kind_Record_Subtype_Definition =>
+ Res := Get_Parent_Type (Res);
+ when others =>
+ Error_Kind ("get_base_type", Res);
+ end case;
+ end loop;
+ end Get_Base_Type;
+
function Is_Anonymous_Type_Definition (Def : Iir) return Boolean is
begin
return Get_Type_Declarator (Def) = Null_Iir;
@@ -1284,17 +1319,6 @@ package body Vhdl.Utils is
end if;
end Get_Denoted_Type_Mark;
- function Get_Parent_Type (Subtyp : Iir) return Iir
- is
- Type_Mark_Name : constant Iir := Get_Subtype_Type_Mark (Subtyp);
- begin
- if Type_Mark_Name = Null_Iir then
- return Get_Base_Type (Subtyp);
- else
- return Get_Type (Get_Named_Entity (Type_Mark_Name));
- end if;
- end Get_Parent_Type;
-
function Get_Base_Element_Declaration (El : Iir) return Iir
is
Rec_Type : constant Iir := Get_Base_Type (Get_Parent (El));
@@ -1625,7 +1649,7 @@ package body Vhdl.Utils is
begin
Res := Create_Iir (Iir_Kind_Array_Subtype_Definition);
Set_Location (Res, Loc);
- Set_Base_Type (Res, Base_Type);
+ Set_Parent_Type (Res, Base_Type);
Set_Element_Subtype (Res, El_Type);
if Get_Kind (Arr_Type) = Iir_Kind_Array_Subtype_Definition then
Set_Resolution_Indication (Res, Get_Resolution_Indication (Arr_Type));
@@ -1705,7 +1729,6 @@ package body Vhdl.Utils is
begin
Res := Create_Error (Orig);
--Set_Expr_Staticness (Res, Locally);
- Set_Base_Type (Res, Res);
Set_Type_Declarator (Res, Null_Iir);
Set_Resolved_Flag (Res, True);
Set_Signal_Type_Flag (Res, True);
diff --git a/src/vhdl/vhdl-utils.ads b/src/vhdl/vhdl-utils.ads
index 6712aa0fa..5cbdc8c25 100644
--- a/src/vhdl/vhdl-utils.ads
+++ b/src/vhdl/vhdl-utils.ads
@@ -160,6 +160,10 @@ package Vhdl.Utils is
-- Clear flag of TOP and all of its callees.
procedure Clear_Seen_Flag (Top : Iir);
+ -- Return the base type of ATYPE. Will always return ATYPE if ATYPE is
+ -- a proper type (and not a subtype).
+ function Get_Base_Type (Atype : Iir) return Iir;
+
-- Return TRUE iff DEF is an anonymous type (or subtype) definition.
-- Note: DEF is required to be a type (or subtype) definition.
-- Note: type (and not subtype) are never anonymous.
@@ -263,10 +267,6 @@ package Vhdl.Utils is
-- Return the type or subtype definition of the SUBTYP type mark.
function Get_Denoted_Type_Mark (Subtyp : Iir) return Iir;
- -- Return the parent type, which is either the type of the type mark, or
- -- the base type if SUBTYP has no type mark.
- function Get_Parent_Type (Subtyp : Iir) return Iir;
-
-- From element declaration or element constraint EL, get the corresponding
-- element declaration in the base record type.
function Get_Base_Element_Declaration (El : Iir) return Iir;
--
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