From ca8803efc8b2c52b813bf22df814c26e139889e2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 30 Jul 2019 20:57:16 +0200 Subject: synth: adjust output for dyn_insert, add dpram2 test. --- src/synth/netlists-disp_vhdl.adb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 95d01102a..800fc585c 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -571,8 +571,8 @@ package body Netlists.Disp_Vhdl is " begin" & NL & " \o0 <= \i0;" & NL & " \o0 (" & - "to_integer (signed (\i2)) * \p0 + (\sp1 + \n0)" & NL & - " downto to_integer (signed (\i2)) * \p0 + (\sp1))" & + "to_integer (\ui2) * \p0 + (\sp1 + \n0)" & NL & + " downto to_integer (\ui2) * \p0 + (\sp1))" & " <= \i1;" & NL & " end process;" & NL, Inst, (0 => Iw - 1)); -- cgit v1.2.3