From 99dbf1376808a1bffb6886811d1585e34673b078 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 8 Feb 2023 11:31:04 +0100 Subject: synth: use same layout for records in memory as translate --- src/simul/simul-vhdl_simul.adb | 2 +- src/synth/elab-vhdl_expr.adb | 12 +-- src/synth/elab-vhdl_objtypes.adb | 208 ++++++++++++++++++++++++++++++++------- src/synth/elab-vhdl_objtypes.ads | 32 ++++-- src/synth/elab-vhdl_types.adb | 14 ++- src/synth/synth-vhdl_aggr.adb | 6 +- src/synth/synth-vhdl_eval.adb | 2 +- src/synth/synth-vhdl_expr.adb | 6 +- src/synth/synth-vhdl_stmts.adb | 15 +-- src/vhdl/vhdl-evaluation.adb | 2 +- 10 files changed, 229 insertions(+), 70 deletions(-) (limited to 'src') diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 53afa715c..5626813a2 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2742,7 +2742,7 @@ package body Simul.Vhdl_Simul is -- Create the type. Bnd := Elab.Vhdl_Types.Create_Bounds_From_Length (R.Idx_Typ.Drange, Len); - Arr_Typ := Create_Array_Type (Bnd, True, El_Typ); + Arr_Typ := Create_Array_Type (Bnd, False, True, El_Typ); -- Allocate the array. Arr := Create_Memory (Arr_Typ); diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb index 2ef7d8982..bfd4aa3aa 100644 --- a/src/synth/elab-vhdl_expr.adb +++ b/src/synth/elab-vhdl_expr.adb @@ -423,18 +423,18 @@ package body Elab.Vhdl_Expr is case Btyp.Kind is when Type_Vector => pragma Assert (El_Typ.Kind in Type_Nets); - Res := Create_Vector_Type (Bnd, Btyp.Arr_El); + Res := Create_Vector_Type (Bnd, False, Btyp.Arr_El); when Type_Unbounded_Vector => pragma Assert (El_Typ.Kind in Type_Nets); - Res := Create_Vector_Type (Bnd, Btyp.Uarr_El); + Res := Create_Vector_Type (Bnd, False, Btyp.Uarr_El); when Type_Array => pragma Assert (Btyp.Alast); pragma Assert (Is_Bounded_Type (Btyp.Arr_El)); - Res := Create_Array_Type (Bnd, True, Btyp.Arr_El); + Res := Create_Array_Type (Bnd, False, True, Btyp.Arr_El); when Type_Unbounded_Array => pragma Assert (Btyp.Ulast); pragma Assert (Is_Bounded_Type (El_Typ)); - Res := Create_Array_Type (Bnd, True, El_Typ); + Res := Create_Array_Type (Bnd, False, True, El_Typ); when others => raise Internal_Error; end case; @@ -584,9 +584,9 @@ package body Elab.Vhdl_Expr is El_Type := Get_Array_Element (Str_Typ); if El_Type.Kind in Type_Nets then - Res_Type := Create_Vector_Type (Bounds, El_Type); + Res_Type := Create_Vector_Type (Bounds, True, El_Type); else - Res_Type := Create_Array_Type (Bounds, True, El_Type); + Res_Type := Create_Array_Type (Bounds, True, True, El_Type); end if; Res := Create_Value_Memory (Res_Type, Current_Pool); diff --git a/src/synth/elab-vhdl_objtypes.adb b/src/synth/elab-vhdl_objtypes.adb index 9c20cc377..745151c2c 100644 --- a/src/synth/elab-vhdl_objtypes.adb +++ b/src/synth/elab-vhdl_objtypes.adb @@ -331,6 +331,8 @@ package body Elab.Vhdl_Objtypes is Is_Signed => False), Al => 0, Is_Global => False, + Is_Static => True, + Is_Bnd_Static => True, Sz => 1, W => 1))); end Create_Bit_Type; @@ -348,6 +350,8 @@ package body Elab.Vhdl_Objtypes is Is_Signed => False), Al => 0, Is_Global => False, + Is_Static => True, + Is_Bnd_Static => True, Sz => 1, W => 1))); end Create_Logic_Type; @@ -373,6 +377,8 @@ package body Elab.Vhdl_Objtypes is Wkind => Wkind_Net, Al => Al, Is_Global => False, + Is_Static => True, + Is_Bnd_Static => True, Sz => Sz, W => W, Drange => Rng))); @@ -387,13 +393,16 @@ package body Elab.Vhdl_Objtypes is Wkind => Wkind_Net, Al => 3, Is_Global => False, + Is_Static => True, + Is_Bnd_Static => True, Sz => 8, W => 64, Frange => Rng))); end Create_Float_Type; - function Create_Vector_Type (Bnd : Bound_Type; El_Type : Type_Acc) - return Type_Acc + function Create_Vector_Type (Bnd : Bound_Type; + Static_Bnd : Boolean; + El_Type : Type_Acc) return Type_Acc is subtype Vector_Type_Type is Type_Type (Type_Vector); function Alloc is new Areapools.Alloc_On_Pool_Addr (Vector_Type_Type); @@ -404,6 +413,8 @@ package body Elab.Vhdl_Objtypes is Wkind => El_Type.Wkind, Al => El_Type.Al, Is_Global => False, + Is_Static => Static_Bnd, + Is_Bnd_Static => Static_Bnd, Sz => El_Type.Sz * Size_Type (Bnd.Len), W => Bnd.Len, Alast => True, @@ -422,6 +433,8 @@ package body Elab.Vhdl_Objtypes is Wkind => El_Type.Wkind, Al => El_Type.Al, Is_Global => False, + Is_Static => False, + Is_Bnd_Static => False, Sz => Size_Type (Len) * El_Type.Sz, W => Len * El_Type.W, Slice_El => El_Type))); @@ -434,20 +447,26 @@ package body Elab.Vhdl_Objtypes is Left => Int32 (Len) - 1, Right => 0, Len => Len), + False, El); end Create_Vec_Type_By_Length; - function Create_Array_Type - (Bnd : Bound_Type; Last : Boolean; El_Type : Type_Acc) return Type_Acc + function Create_Array_Type (Bnd : Bound_Type; + Static_Bnd : Boolean; + Last : Boolean; + El_Type : Type_Acc) return Type_Acc is subtype Array_Type_Type is Type_Type (Type_Array); function Alloc is new Areapools.Alloc_On_Pool_Addr (Array_Type_Type); + Is_Static : constant Boolean := Static_Bnd and El_Type.Is_Static; begin return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Array, Wkind => El_Type.Wkind, Al => El_Type.Al, Is_Global => False, + Is_Static => Is_Static, + Is_Bnd_Static => Static_Bnd, Sz => El_Type.Sz * Size_Type (Bnd.Len), W => El_Type.W * Bnd.Len, Abound => Bnd, @@ -455,8 +474,10 @@ package body Elab.Vhdl_Objtypes is Arr_El => El_Type))); end Create_Array_Type; - function Create_Array_Unbounded_Type - (Bnd : Bound_Type; Last : Boolean; El_Type : Type_Acc) return Type_Acc + function Create_Array_Unbounded_Type (Bnd : Bound_Type; + Static_Bnd : Boolean; + Last : Boolean; + El_Type : Type_Acc) return Type_Acc is subtype Array_Unbounded_Type_Type is Type_Type (Type_Array_Unbounded); function Alloc is @@ -467,6 +488,8 @@ package body Elab.Vhdl_Objtypes is Wkind => El_Type.Wkind, Al => El_Type.Al, Is_Global => False, + Is_Static => False, + Is_Bnd_Static => Static_Bnd, Sz => 0, W => 0, Abound => Bnd, @@ -484,6 +507,8 @@ package body Elab.Vhdl_Objtypes is Wkind => El_Type.Wkind, Al => El_Type.Al, Is_Global => False, + Is_Static => False, + Is_Bnd_Static => False, Sz => 0, W => 0, Ulast => Last, @@ -495,10 +520,11 @@ package body Elab.Vhdl_Objtypes is (Parent : Type_Acc; El : Type_Acc) return Type_Acc is begin if Parent.Alast then - return Create_Array_Type (Parent.Abound, True, El); + return Create_Array_Type + (Parent.Abound, Parent.Is_Bnd_Static, True, El); else return Create_Array_Type - (Parent.Abound, False, + (Parent.Abound, Parent.Is_Bnd_Static, False, Create_Array_From_Array_Unbounded (Parent.Arr_El, El)); end if; end Create_Array_From_Array_Unbounded; @@ -513,6 +539,8 @@ package body Elab.Vhdl_Objtypes is Wkind => El_Type.Wkind, Al => El_Type.Al, Is_Global => False, + Is_Static => False, + Is_Bnd_Static => False, Sz => 0, W => 0, Ulast => True, @@ -617,62 +645,161 @@ package body Elab.Vhdl_Objtypes is return (Off + Mask) and not Mask; end Align; - function Create_Record_Type (Els : Rec_El_Array_Acc) return Type_Acc + procedure Layout_Element_Mem (El : in out Rec_El_Type; + Sz : in out Size_Type; + Al : in out Palign_Type) is + begin + -- For memory. + Al := Palign_Type'Max (Al, El.Typ.Al); + Sz := Align (Sz, El.Typ.Al); + El.Offs.Mem_Off := Sz; + Sz := Sz + El.Typ.Sz; + end Layout_Element_Mem; + + procedure Layout_Element_Net (El : in out Rec_El_Type; + W : in out Uns32; + Wkind : in out Wkind_Type) is + begin + -- For nets. + El.Offs.Net_Off := W; + if El.Typ.Wkind /= Wkind_Net then + Wkind := Wkind_Undef; + end if; + W := W + El.Typ.W; + end Layout_Element_Net; + + function Create_Record_Type (Parent_Typ : Type_Acc; + Els : Rec_El_Array_Acc) return Type_Acc is subtype Record_Type_Type is Type_Type (Type_Record); function Alloc is new Areapools.Alloc_On_Pool_Addr (Record_Type_Type); + Base : Type_Acc; + Base_Els : Rec_El_Array_Acc; Wkind : Wkind_Type; W : Uns32; Al : Palign_Type; Sz : Size_Type; + Res : Type_Acc; begin -- Layout the record. + if Parent_Typ = null then + Al := 0; + Sz := 0; + -- First elements with static types, then the others. + for Static in reverse Boolean loop + for I in Els.E'Range loop + declare + El : Rec_El_Type renames Els.E (I); + begin + if El.Typ.Is_Static = Static then + Layout_Element_Mem (El, Sz, Al); + end if; + end; + end loop; + end loop; + Sz := Align (Sz, Al); + + else + Base := Parent_Typ.Rec_Base; + Base_Els := Base.Rec; + Al := Base.Al; + Sz := Base.Sz; + -- Only the non-static types. + for I in Els.E'Range loop + if Base_Els.E (I).Typ.Is_Static then + Els.E (I).Offs.Mem_Off := Base_Els.E (I).Offs.Mem_Off; + else + Layout_Element_Mem (Els.E (I), Sz, Al); + end if; + end loop; + end if; + Sz := Align (Sz, Al); + + -- Layout nets. Wkind := Wkind_Net; - Al := 0; - Sz := 0; W := 0; for I in Els.E'Range loop - declare - E : Rec_El_Type renames Els.E (I); - begin - -- For nets. - E.Offs.Net_Off := W; - if E.Typ.Wkind /= Wkind_Net then - Wkind := Wkind_Undef; - end if; - W := W + E.Typ.W; - - -- For memory. - Al := Palign_Type'Max (Al, E.Typ.Al); - Sz := Align (Sz, E.Typ.Al); - E.Offs.Mem_Off := Sz; - Sz := Sz + E.Typ.Sz; - end; + Layout_Element_Net (Els.E (I), W, Wkind); end loop; - Sz := Align (Sz, Al); - - return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Record, + Res := To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Record, Wkind => Wkind, Al => Al, Is_Global => False, + Is_Static => False, + Is_Bnd_Static => False, Sz => Sz, W => W, + Rec_Base => null, Rec => Els))); + if Parent_Typ = null then + Res.Rec_Base := Res; + else + Res.Rec_Base := Base; + end if; + + return Res; end Create_Record_Type; - function Create_Unbounded_Record (Els : Rec_El_Array_Acc) return Type_Acc + function Create_Unbounded_Record (Parent_Typ : Type_Acc; + Els : Rec_El_Array_Acc) return Type_Acc is subtype Unbounded_Record_Type_Type is Type_Type (Type_Unbounded_Record); function Alloc is new Areapools.Alloc_On_Pool_Addr (Unbounded_Record_Type_Type); + Base : Type_Acc; + Base_Els : Rec_El_Array_Acc; + Wkind : Wkind_Type; + W : Uns32; + Al : Palign_Type; + Sz : Size_Type; + Res : Type_Acc; begin - return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Unbounded_Record, - Wkind => Wkind_Net, - Al => 0, + -- Layout the record. + Wkind := Wkind_Net; + W := 0; + if Parent_Typ = null then + -- Layout only static elements. + Al := 0; + Sz := 0; + for I in Els.E'Range loop + declare + El : Rec_El_Type renames Els.E (I); + begin + if El.Typ.Is_Static then + Layout_Element_Mem (El, Sz, Al); + El.Offs.Net_Off := 0; + else + El.Offs := No_Value_Offsets; + end if; + end; + end loop; + else + -- Copy layout of base type. + Base := Parent_Typ.Rec_Base; + Base_Els := Base.Rec; + Al := Base.Al; + Sz := Base.Sz; + for I in Els.E'Range loop + Els.E (I).Offs := Base_Els.E (I).Offs; + end loop; + end if; + + Res := To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Unbounded_Record, + Wkind => Wkind, + Al => Al, Is_Global => False, - Sz => 0, - W => 0, + Is_Static => False, + Is_Bnd_Static => False, + Sz => Sz, + W => W, + Rec_Base => null, Rec => Els))); + if Parent_Typ = null then + Res.Rec_Base := Res; + else + Res.Rec_Base := Parent_Typ.Rec_Base; + end if; + return Res; end Create_Unbounded_Record; -- Compute size and alignment for bounds of TYP. @@ -809,6 +936,8 @@ package body Elab.Vhdl_Objtypes is Wkind => Wkind_Sim, Al => Heap_Ptr_Al, Is_Global => False, + Is_Static => True, + Is_Bnd_Static => True, Sz => Heap_Ptr_Sz, W => 1, Acc_Acc => Acc_Type, @@ -832,6 +961,8 @@ package body Elab.Vhdl_Objtypes is Wkind => Wkind_Sim, Al => 2, Is_Global => False, + Is_Static => True, + Is_Bnd_Static => True, Sz => 4, W => 1, File_Typ => File_Type, @@ -847,6 +978,8 @@ package body Elab.Vhdl_Objtypes is Wkind => Wkind_Sim, Al => 2, Is_Global => False, + Is_Static => True, + Is_Bnd_Static => True, Sz => 4, W => 1))); end Create_Protected_Type; @@ -1223,6 +1356,9 @@ package body Elab.Vhdl_Objtypes is Res.Rec.E (I) := (Offs => T.Rec.E (I).Offs, Typ => Unshare (T.Rec.E (I).Typ, Pool)); end loop; + if T.Rec_Base = T then + Res.Rec_Base := Res; + end if; when Type_Access => if T.Acc_Acc /= null then Res.Acc_Acc := Unshare (T.Acc_Acc, Pool); diff --git a/src/synth/elab-vhdl_objtypes.ads b/src/synth/elab-vhdl_objtypes.ads index 8862f44c7..12c770eb5 100644 --- a/src/synth/elab-vhdl_objtypes.ads +++ b/src/synth/elab-vhdl_objtypes.ads @@ -164,6 +164,11 @@ package Elab.Vhdl_Objtypes is -- unshared. Is_Global : Boolean; + -- True if the size of an object is known at compile time. + -- Used for layout of records. + Is_Static : Boolean; + Is_Bnd_Static : Boolean; + -- Number of bytes (when in memory) for this type. Sz : Size_Type; @@ -196,6 +201,8 @@ package Elab.Vhdl_Objtypes is Uarr_Idx : Type_Acc; when Type_Record | Type_Unbounded_Record => + -- The base type, used to have compatible layouts. + Rec_Base : Type_Acc; -- The first elements is in the LSBs of the net. Rec : Rec_El_Array_Acc; when Type_Access => @@ -270,23 +277,32 @@ package Elab.Vhdl_Objtypes is function Create_Float_Type (Rng : Float_Range_Type) return Type_Acc; function Create_Vec_Type_By_Length (Len : Uns32; El : Type_Acc) return Type_Acc; - function Create_Vector_Type (Bnd : Bound_Type; El_Type : Type_Acc) - return Type_Acc; + function Create_Vector_Type (Bnd : Bound_Type; + Static_Bnd : Boolean; + El_Type : Type_Acc) return Type_Acc; function Create_Unbounded_Vector (El_Type : Type_Acc; Idx : Type_Acc) return Type_Acc; function Create_Slice_Type (Len : Uns32; El_Type : Type_Acc) return Type_Acc; - function Create_Array_Type - (Bnd : Bound_Type; Last : Boolean; El_Type : Type_Acc) return Type_Acc; - function Create_Array_Unbounded_Type - (Bnd : Bound_Type; Last : Boolean; El_Type : Type_Acc) return Type_Acc; + function Create_Array_Type (Bnd : Bound_Type; + Static_Bnd : Boolean; + Last : Boolean; + El_Type : Type_Acc) return Type_Acc; + function Create_Array_Unbounded_Type (Bnd : Bound_Type; + Static_Bnd : Boolean; + Last : Boolean; + El_Type : Type_Acc) return Type_Acc; function Create_Unbounded_Array (Idx : Type_Acc; Last : Boolean; El_Type : Type_Acc) return Type_Acc; function Create_Rec_El_Array (Nels : Iir_Index32) return Rec_El_Array_Acc; - function Create_Record_Type (Els : Rec_El_Array_Acc) return Type_Acc; - function Create_Unbounded_Record (Els : Rec_El_Array_Acc) return Type_Acc; + -- PARENT_TYP is a parent type or null to create a base type. + -- Used to have the same layout. + function Create_Record_Type (Parent_Typ : Type_Acc; + Els : Rec_El_Array_Acc) return Type_Acc; + function Create_Unbounded_Record (Parent_Typ : Type_Acc; + Els : Rec_El_Array_Acc) return Type_Acc; -- ACC_TYPE can be null for an incomplete type. function Create_Access_Type (Acc_Type : Type_Acc) return Type_Acc; diff --git a/src/synth/elab-vhdl_types.adb b/src/synth/elab-vhdl_types.adb index 75f27a888..cec15cae2 100644 --- a/src/synth/elab-vhdl_types.adb +++ b/src/synth/elab-vhdl_types.adb @@ -310,9 +310,9 @@ package body Elab.Vhdl_Types is end loop; if Bounded then - return Create_Record_Type (Rec_Els); + return Create_Record_Type (Parent_Typ, Rec_Els); else - return Create_Unbounded_Record (Rec_Els); + return Create_Unbounded_Record (Parent_Typ, Rec_Els); end if; end Synth_Record_Type_Definition; @@ -617,12 +617,14 @@ package body Elab.Vhdl_Types is declare St_El : Node; Bnd : Bound_Type; + Bnd_Static : Boolean; begin St_El := Get_Index_Type (St_Indexes, 0); Bnd := Synth_Bounds_From_Range (Syn_Inst, St_El); + Bnd_Static := Get_Type_Staticness (St_El) = Locally; Check_Bound_Compatibility (Syn_Inst, St_El, Bnd, Parent_Typ.Uarr_Idx); - return Create_Vector_Type (Bnd, El_Typ); + return Create_Vector_Type (Bnd, Bnd_Static, El_Typ); end; else -- An alias. @@ -639,11 +641,13 @@ package body Elab.Vhdl_Types is Res_Typ : Type_Acc; Bnd : Bound_Type; P : Type_Acc; + Bnd_Static : Boolean; begin Res_Typ := El_Typ; for I in reverse Flist_First .. Flist_Last (St_Indexes) loop St_El := Get_Index_Type (St_Indexes, I); Bnd := Synth_Bounds_From_Range (Syn_Inst, St_El); + Bnd_Static := Get_Type_Staticness (St_El) = Locally; -- Get parent index. P := Parent_Typ; for J in Flist_First + 1 .. I loop @@ -653,10 +657,10 @@ package body Elab.Vhdl_Types is (Syn_Inst, St_El, Bnd, P.Uarr_Idx); if El_Bounded then Res_Typ := Create_Array_Type - (Bnd, Res_Typ = El_Typ, Res_Typ); + (Bnd, Bnd_Static, Res_Typ = El_Typ, Res_Typ); else Res_Typ := Create_Array_Unbounded_Type - (Bnd, Res_Typ = El_Typ, Res_Typ); + (Bnd, Bnd_Static, Res_Typ = El_Typ, Res_Typ); end if; end loop; return Res_Typ; diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb index 650510e0e..1abe5a7b2 100644 --- a/src/synth/synth-vhdl_aggr.adb +++ b/src/synth/synth-vhdl_aggr.adb @@ -614,9 +614,9 @@ package body Synth.Vhdl_Aggr is (Aggr_Typ.Uarr_Idx.Drange, Iir_Index32 (Len)); case Aggr_Typ.Kind is when Type_Unbounded_Vector => - Res_Typ := Create_Vector_Type (Bnd, El_Typ); + Res_Typ := Create_Vector_Type (Bnd, False, El_Typ); when Type_Unbounded_Array => - Res_Typ := Create_Array_Type (Bnd, True, El_Typ); + Res_Typ := Create_Array_Type (Bnd, False, True, El_Typ); when others => raise Internal_Error; end case; @@ -661,7 +661,7 @@ package body Synth.Vhdl_Aggr is Els_Typ.E (I).Typ := Tab_Res (Tab_Res'Last - Nat32 (I) + 1).Typ; end loop; - Res_Typ := Create_Record_Type (Els_Typ); + Res_Typ := Create_Record_Type (Aggr_Type, Els_Typ); end; when Type_Record => Res_Typ := Aggr_Type; diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index ec3b19e99..23bb3dac8 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -751,7 +751,7 @@ package body Synth.Vhdl_Eval is begin Bnd := (Dir => Dir_To, Left => 1, Right => Int32 (Len), Len => Uns32 (Len)); - Typ := Create_Array_Type (Bnd, True, Styp.Uarr_El); + Typ := Create_Array_Type (Bnd, True, True, Styp.Uarr_El); Res := Create_Memory (Typ); for I in Str'Range loop diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 80d1a22fc..6433fa616 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -539,9 +539,11 @@ package body Synth.Vhdl_Expr is then case Utype.Kind is when Type_Unbounded_Array => - return Create_Array_Type (Stype.Abound, Utype.Ulast, Res_El); + return Create_Array_Type + (Stype.Abound, False, Utype.Ulast, Res_El); when Type_Unbounded_Vector => - return Create_Vector_Type (Stype.Abound, Res_El); + return Create_Vector_Type + (Stype.Abound, False, Res_El); when others => raise Internal_Error; end case; diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 1cc9e24a8..fcf4fb498 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -411,10 +411,10 @@ package body Synth.Vhdl_Stmts is -- Compute the type. case Base_Typ.Kind is when Type_Unbounded_Vector => - Res := Create_Vector_Type (Bnd, Base_Typ.Uarr_El); + Res := Create_Vector_Type (Bnd, False, Base_Typ.Uarr_El); when Type_Unbounded_Array => pragma Assert (Base_Typ.Ulast); - Res := Create_Array_Type (Bnd, True, Base_Typ.Uarr_El); + Res := Create_Array_Type (Bnd, False, True, Base_Typ.Uarr_El); when others => raise Internal_Error; end case; @@ -2111,7 +2111,7 @@ package body Synth.Vhdl_Stmts is Typ => Copy_Unbounded_Type (Typ.Rec.E (I).Typ, Base.Rec.E (I).Typ)); end loop; - return Create_Unbounded_Record (Els); + return Create_Unbounded_Record (Typ.Rec_Base, Els); end; when Type_Unbounded_Array => return Create_Unbounded_Array @@ -2119,8 +2119,8 @@ package body Synth.Vhdl_Stmts is Base.Uarr_El)); when Type_Array_Unbounded => return Create_Array_Unbounded_Type - (Typ.Abound, Typ.Alast, Copy_Unbounded_Type (Typ.Uarr_El, - Base.Uarr_El)); + (Typ.Abound, Typ.Is_Bnd_Static, Typ.Alast, + Copy_Unbounded_Type (Typ.Uarr_El, Base.Uarr_El)); when Type_Unbounded_Vector => return Create_Unbounded_Vector (Typ.Uarr_Idx, Typ.Uarr_El); when Type_Slice => @@ -2369,14 +2369,15 @@ package body Synth.Vhdl_Stmts is case Type_Composite (Formal_Typ.Kind) is when Type_Unbounded_Record => -- TODO: unbounded record with unbounded elements. - Formal_Typ := Create_Record_Type (Formal_Typ.Rec); + Formal_Typ := Create_Record_Type (Formal_Typ, Formal_Typ.Rec); when Type_Unbounded_Array | Type_Unbounded_Vector => raise Internal_Error; when Type_Array_Unbounded => pragma Assert (Formal_Typ.Alast); -- TODO. Formal_Typ := Create_Array_Type - (Formal_Typ.Abound, Formal_Typ.Alast, Formal_Typ.Arr_El); + (Formal_Typ.Abound, False, Formal_Typ.Alast, + Formal_Typ.Arr_El); when Type_Array | Type_Vector | Type_Record => diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index 31b44768b..45de6c827 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -841,7 +841,7 @@ package body Vhdl.Evaluation is Res_Rng := Convert_Discrete_Range (Get_Range_Constraint (Idx)); return Create_Vector_Type - (Synth_Bounds_From_Range (Res_Rng), El_Typ); + (Synth_Bounds_From_Range (Res_Rng), True, El_Typ); end; when others => -- cgit v1.2.3