From 9756bb517abcbeaa3156e1dcc18081ac0b651d8d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 8 Jul 2019 07:51:12 +0200
Subject: vhdl simul-elaboration: minor rewrite.

---
 src/vhdl/simulate/simul-elaboration.adb | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index fe89d48c7..b4f690ab4 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -1664,7 +1664,7 @@ package body Simul.Elaboration is
             Arch : Iir;
             Config : Iir;
          begin
-            case Get_Kind (Aspect) is
+            case Iir_Kinds_Entity_Aspect (Get_Kind (Aspect)) is
                when Iir_Kind_Entity_Aspect_Entity =>
                   Arch := Get_Architecture (Aspect);
                   if Arch = Null_Iir then
@@ -1681,8 +1681,6 @@ package body Simul.Elaboration is
                     (Get_Block_Configuration (Config));
                when Iir_Kind_Entity_Aspect_Open =>
                   return;
-               when others =>
-                  raise Internal_Error;
             end case;
             Config := Get_Block_Configuration (Config);
 
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