From 9034e7fba36540f0f38d9aa55e91391c5804d649 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 9 Aug 2022 21:44:27 +0200 Subject: synth-vhdl_oper.adb: fix mul uns uns. Fix #2169 --- src/synth/synth-vhdl_oper.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 9cc3f5e95..920729c44 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1233,7 +1233,7 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv => -- "*" (unsigned, unsigned) return Synth_Dyadic_Xxx_Xxx - (Ctxt, Id_Smul, Left.Typ.W + Right.Typ.W, + (Ctxt, Id_Umul, Left.Typ.W + Right.Typ.W, Left, Right, False, False, Expr); when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat => -- "*" (unsigned, natural) -- cgit v1.2.3