From 8654319ba2be19b5a17898a25e9fb562080af284 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 27 Aug 2021 06:57:51 +0200 Subject: std_names: add name keep. --- src/std_names.adb | 1 + src/std_names.ads | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/std_names.adb b/src/std_names.adb index ffbfce1ef..ceabfec97 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -685,6 +685,7 @@ package body Std_Names is Def ("anyseq", Name_Anyseq); Def ("gclk", Name_Gclk); Def ("loc", Name_Loc); + Def ("keep", Name_Keep); -- Verilog directives Def ("define", Name_Define); diff --git a/src/std_names.ads b/src/std_names.ads index 45558cb48..4022a7493 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -770,7 +770,8 @@ package Std_Names is Name_Anyseq : constant Name_Id := Name_First_Synthesis + 003; Name_Gclk : constant Name_Id := Name_First_Synthesis + 004; Name_Loc : constant Name_Id := Name_First_Synthesis + 005; - Name_Last_Synthesis : constant Name_Id := Name_Loc; + Name_Keep : constant Name_Id := Name_First_Synthesis + 006; + Name_Last_Synthesis : constant Name_Id := Name_Keep; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1; -- cgit v1.2.3