From 84bf6bee9480a93b789a4d1ffee380117e3ab177 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 14 Jan 2023 21:24:58 +0100
Subject: simul: disable --trace-signals

---
 src/simul/simul-vhdl_simul.adb | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src')

diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 7d1a4312a..c03da08f1 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -4128,8 +4128,12 @@ package body Simul.Vhdl_Simul is
       pragma Assert (Areapools.Is_Empty (Expr_Pool));
       pragma Assert (Areapools.Is_Empty (Process_Pool));
 
+      --  Copy flag.
       Synth.Flags.Severity_Level := Grt.Options.Severity_Level;
 
+      --  Not supported.
+      Grt.Options.Trace_Signals := False;
+
       if Flag_Interractive then
          Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
       end if;
-- 
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