From 693466dceafbbca9cf060e4ee8e43b8abf1173cd Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 19 Oct 2022 05:24:42 +0200 Subject: synth-vhdl_oper: handle and_reduce. Fix #2224 --- src/synth/synth-vhdl_oper.adb | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 1bbfbb133..960747266 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -2129,7 +2129,7 @@ package body Synth.Vhdl_Oper is return Synth_Dyadic_Int_Sgn (Ctxt, Id_Smax, L, R, Expr); when Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Slv - | Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv => + | Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv => declare N : Net; begin @@ -2137,6 +2137,15 @@ package body Synth.Vhdl_Oper is Set_Location (N, Expr); return Create_Value_Net (N, Res_Typ); end; + when Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Suv => + declare + N : Net; + begin + N := Build_Reduce (Ctxt, Id_Red_And, Get_Net (Ctxt, L)); + Set_Location (N, Expr); + return Create_Value_Net (N, Res_Typ); + end; when Iir_Predefined_Ieee_Numeric_Std_Match_Suv | Iir_Predefined_Ieee_Numeric_Std_Match_Slv => -- cgit v1.2.3