From 68978a5a6bc78b9d71985648ae4976119d3c640c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 5 Jun 2022 09:08:27 +0200 Subject: synth-vhdl_expr: adjust max computation for memidx. Fix #2073 --- src/synth/netlists-gates.ads | 4 ++-- src/synth/synth-vhdl_expr.adb | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 6e78054af..305bd5158 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -264,8 +264,8 @@ package Netlists.Gates is -- addidx. -- Inputs: 0: index -- Params: 0: step - -- 1: max - -- OUT := IN0 * STEP, IN0 < MAX + -- 1: max (maximum value for index, so length - 1). + -- OUT := IN0 * STEP, IN0 <= MAX Id_Memidx : constant Module_Id := 90; -- Combine (simply add) indexes for dynamic insert or extract. diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index d58399021..75d7d7e78 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -1258,7 +1258,7 @@ package body Synth.Vhdl_Expr is -- max so that max*step+wd <= len - off -- max <= (len - off - wd) / step Max := (Pfx_Bnd.Len - Off.Net_Off - Res_Bnd.Len) / Step; - if Clog2 (Uns64 (Max)) > Natural (Inp_W) then + if Max > 2**Natural (Inp_W) - 1 then -- The width of Inp limits the max. Max := 2**Natural (Inp_W) - 1; end if; -- cgit v1.2.3