From 677d7c1971e3b35709eec2e802e7935cee02455d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 1 Oct 2022 18:18:19 +0200 Subject: simul: minor rewrite --- src/simul/simul-vhdl_simul.adb | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index bee671e1b..64efe82fa 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -528,8 +528,7 @@ package body Simul.Vhdl_Simul is Synth_Subprogram_Back_Association (Process.Instance, Caller_Inst, Get_Interface_Declaration_Chain (Imp), - Get_Parameter_Association_Chain - (Get_Procedure_Call (Stmt))); + Get_Parameter_Association_Chain (Get_Procedure_Call (Stmt))); Process.Instance := Caller_Inst; -- TODO: free old inst. end Finish_Procedure_Call; @@ -587,7 +586,7 @@ package body Simul.Vhdl_Simul is Finish_Procedure_Call (Process, Parent, Stmt); exit when Stmt = Null_Node; when others => - Vhdl.Errors.Error_Kind ("next_statement", Parent); + Vhdl.Errors.Error_Kind ("next_parent_statement", Parent); end case; N_Stmt := Get_Chain (Stmt); -- cgit v1.2.3