From 5e4358bfee56ee068745923d167f466a4e950074 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 11 Apr 2020 15:22:51 +0200
Subject: synth: initialize variables with a static value.

---
 src/synth/synth-decls.adb | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index f0ccf71db..bf84ed41b 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -724,6 +724,7 @@ package body Synth.Decls is
       --  Slot : constant Object_Slot_Type := Get_Info (Decl).Slot;
       Init : Valtyp;
       Obj_Typ : Type_Acc;
+      Wid : Wire_Id;
    begin
       Synth_Declaration_Type (Syn_Inst, Decl);
       Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl));
@@ -747,10 +748,14 @@ package body Synth.Decls is
          else
             Create_Wire_Object (Syn_Inst, Wire_Variable, Decl);
             Create_Var_Wire (Syn_Inst, Decl, Init);
+            Wid := Get_Value (Syn_Inst, Decl).Val.W;
             if Is_Subprg then
-               Phi_Assign_Net
-                 (Get_Build (Syn_Inst),
-                  Get_Value (Syn_Inst, Decl).Val.W, Get_Net (Init), 0);
+               if Is_Static (Init.Val) then
+                  Phi_Assign_Static (Wid, Get_Memtyp (Init));
+               else
+                  Phi_Assign_Net
+                    (Get_Build (Syn_Inst), Wid, Get_Net (Init), 0);
+               end if;
             end if;
          end if;
       end if;
-- 
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