From 44095bf454b98b580ff41c92da52ce431a45828d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 1 Oct 2016 06:50:34 +0200 Subject: Emit error message during analysis for missing generic association. --- src/vhdl/sem.adb | 11 ++++------- src/vhdl/translate/trans-chap5.adb | 1 + 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/vhdl/sem.adb b/src/vhdl/sem.adb index 66e81d135..9e57ec0e2 100644 --- a/src/vhdl/sem.adb +++ b/src/vhdl/sem.adb @@ -378,13 +378,10 @@ package body Sem is -- GHDL: for a direct instantiation, follow rules of -- LRM 1.1.1.1 Generic and LRM 1.1.1.2 Ports. - if Flags.Vhdl_Std = Vhdl_87 - or else Get_Kind (Inter_Parent) = Iir_Kind_Entity_Declaration - then - Miss := Missing_Generic; - else - Miss := Missing_Allowed; - end if; + -- The difference between 87 and 93 is simply a clarification: + -- missing association are left open, but need a default + -- expression in the formal declaration. + Miss := Missing_Generic; when Iir_Kind_Binding_Indication => -- LRM 5.2.1.2 Generic map and port map aspects Miss := Missing_Allowed; diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index c86f34602..f6a11be0f 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -742,6 +742,7 @@ package body Trans.Chap5 is declare Value : constant Iir := Get_Default_Value (Formal); begin + pragma Assert (Is_Valid (Value)); Set_Map_Env (Formal_Env); Chap4.Elab_Object_Value (Formal, Value); Chap9.Destroy_Types (Value); -- cgit v1.2.3