From 3f8c71fe2fe6dc7e2a6532260284ff52f9e65eb2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 27 Aug 2021 07:56:18 +0200
Subject: synth: do not remove signals with a keep attribute.

For ghdl/ghdl-yosys-plugin#154
---
 src/synth/netlists-cleanup.adb | 29 +++++++++++++++++++++++++++++
 src/synth/synth-vhdl_stmts.adb |  3 ++-
 2 files changed, 31 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/synth/netlists-cleanup.adb b/src/synth/netlists-cleanup.adb
index d7d74b83d..8436793a8 100644
--- a/src/synth/netlists-cleanup.adb
+++ b/src/synth/netlists-cleanup.adb
@@ -16,6 +16,8 @@
 --  You should have received a copy of the GNU General Public License
 --  along with this program.  If not, see <gnu.org/licenses>.
 
+with Std_Names;
+
 with Netlists.Utils; use Netlists.Utils;
 with Netlists.Gates;
 
@@ -169,6 +171,28 @@ package body Netlists.Cleanup is
       end loop;
    end Remove_Output_Gates;
 
+   function Has_Keep (Inst : Instance) return Boolean
+   is
+      Attr : Attribute;
+      Val : Pval;
+   begin
+      if not Has_Attribute (Inst) then
+         return False;
+      end if;
+
+      Attr := Get_First_Attribute (Inst);
+      while Attr /= No_Attribute loop
+         if Get_Attribute_Name (Attr) = Std_Names.Name_Keep then
+            Val := Get_Attribute_Pval (Attr);
+            pragma Assert (Get_Pval_Length (Val) = 1);
+            return Read_Pval (Val, 0) = (1, 0);
+         end if;
+         Attr := Get_Attribute_Next (Attr);
+      end loop;
+
+      return False;
+   end Has_Keep;
+
    procedure Insert_Mark_And_Sweep (Inspect : in out Instance_Tables.Instance;
                                     Inst : Instance) is
    begin
@@ -205,6 +229,11 @@ package body Netlists.Cleanup is
                | Id_User_Parameters =>
                --  Always keep user modules.
                Insert_Mark_And_Sweep (Inspect, Inst);
+            when Id_Signal
+              | Id_Isignal =>
+               if Has_Keep (Inst) then
+                  Insert_Mark_And_Sweep (Inspect, Inst);
+               end if;
             when others =>
                null;
          end case;
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 2634af688..bfa3db4be 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -3749,7 +3749,8 @@ package body Synth.Vhdl_Stmts is
                Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyconst);
             when Name_Anyseq =>
                Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyseq);
-            when Name_Loc =>
+            when Name_Loc
+               | Name_Keep =>
                --  Applies to nets/ports.
                null;
             when others =>
-- 
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