From 3bf136140b218a3f9191ba6cef319bede7bf6425 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 4 Dec 2020 07:51:12 +0100 Subject: synth-oper: simplify synth_dyadic_vec_log. For #1520 --- src/synth/synth-oper.adb | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 3a5c0edda..8fded25f7 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -409,18 +409,12 @@ package body Synth.Oper is V : constant Net := Get_Net (Ctxt, Vec); L : constant Net := Get_Net (Ctxt, Log); Wd : constant Width := Get_Width (V); + Lv : Net; Res : Net; - N : Net; - Inst : Instance; begin - Res := Build_Concatn (Ctxt, Wd, Wd); - Inst := Get_Net_Parent (Res); - for I in 1 .. Wd loop - N := Build2_Extract (Ctxt, V, I - 1, 1); - N := Build_Dyadic (Ctxt, Id, N, L); - Set_Location (N, Expr); - Connect (Get_Input (Inst, Port_Nbr (Wd - I)), N); - end loop; + Lv := Build2_Sresize (Ctxt, L, Wd, Get_Location (Expr)); + Res := Build_Dyadic (Ctxt, Id, V, Lv); + Set_Location (Res, Expr); return Create_Value_Net (Res, Create_Res_Bound (Vec)); end Synth_Dyadic_Vec_Log; -- cgit v1.2.3