From 299333e4c12e27fa456a73fa0baeedd1f2f9ec30 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 18 Feb 2022 06:39:24 +0100 Subject: elab-vhdl_values.adb: fix a typo. Fix #1968 --- src/synth/elab-vhdl_values.adb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb index 90e72f223..017edc700 100644 --- a/src/synth/elab-vhdl_values.adb +++ b/src/synth/elab-vhdl_values.adb @@ -246,9 +246,9 @@ package body Elab.Vhdl_Values is Res.Val.Mem (I - 1) := Src.Val.Mem (I - 1); end loop; when Value_Net => - Res := (Src.Typ, Create_Value_Net (Src.Val.S)); + Res := (Src.Typ, Create_Value_Net (Src.Val.N)); when Value_Wire => - Res := (Src.Typ, Create_Value_Wire (Src.Val.S)); + Res := (Src.Typ, Create_Value_Wire (Src.Val.N)); when Value_File => Res := Create_Value_File (Src.Typ, Src.Val.File); when Value_Signal => -- cgit v1.2.3