From 26d9756273a66c4bd359b89db4829edcdb30e522 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 6 Jun 2022 08:35:16 +0200 Subject: vhdl-ieee-math_real: recognize more operations --- src/vhdl/vhdl-ieee-math_real.adb | 37 ++++++++++++++++++++++++++----------- src/vhdl/vhdl-nodes.ads | 20 +++++++++++++++++++- 2 files changed, 45 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index d11030d49..1881bb322 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -16,11 +16,13 @@ with Std_Names; use Std_Names; +with Vhdl.Std_Package; + package body Vhdl.Ieee.Math_Real is procedure Extract_Declarations (Pkg : Iir_Package_Declaration) is Decl : Iir; - Predef : Iir_Predefined_Functions; + Def : Iir_Predefined_Functions; begin Math_Real_Pkg := Pkg; @@ -36,28 +38,41 @@ package body Vhdl.Ieee.Math_Real is case Get_Kind (Decl) is when Iir_Kind_Function_Declaration => - Predef := Iir_Predefined_None; + Def := Iir_Predefined_None; case Get_Identifier (Decl) is + when Name_Mod => + Def := Iir_Predefined_Ieee_Math_Real_Mod; when Name_Ceil => - Predef := Iir_Predefined_Ieee_Math_Real_Ceil; + Def := Iir_Predefined_Ieee_Math_Real_Ceil; when Name_Floor => - Predef := Iir_Predefined_Ieee_Math_Real_Floor; + Def := Iir_Predefined_Ieee_Math_Real_Floor; when Name_Round => - Predef := Iir_Predefined_Ieee_Math_Real_Round; + Def := Iir_Predefined_Ieee_Math_Real_Round; when Name_Log2 => - Predef := Iir_Predefined_Ieee_Math_Real_Log2; + Def := Iir_Predefined_Ieee_Math_Real_Log2; when Name_Sin => - Predef := Iir_Predefined_Ieee_Math_Real_Sin; + Def := Iir_Predefined_Ieee_Math_Real_Sin; when Name_Cos => - Predef := Iir_Predefined_Ieee_Math_Real_Cos; + Def := Iir_Predefined_Ieee_Math_Real_Cos; when Name_Arctan => - Predef := Iir_Predefined_Ieee_Math_Real_Arctan; + Def := Iir_Predefined_Ieee_Math_Real_Arctan; when Name_Op_Exp => - Predef := Iir_Predefined_Ieee_Math_Real_Pow; + declare + use Vhdl.Std_Package; + Inter : constant Iir := + Get_Interface_Declaration_Chain (Decl); + Itype : constant Iir := Get_Type (Inter); + begin + if Itype = Integer_Subtype_Definition then + Def := Iir_Predefined_Ieee_Math_Real_Pow_Int_Real; + elsif Itype = Real_Subtype_Definition then + Def := Iir_Predefined_Ieee_Math_Real_Pow_Real_Real; + end if; + end; when others => null; end case; - Set_Implicit_Definition (Decl, Predef); + Set_Implicit_Definition (Decl, Def); when Iir_Kind_Constant_Declaration => null; when others => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 970063e64..f9b29cf78 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -6049,13 +6049,31 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Math_Real_Floor, Iir_Predefined_Ieee_Math_Real_Round, Iir_Predefined_Ieee_Math_Real_Trunc, + Iir_Predefined_Ieee_Math_Real_Mod, + Iir_Predefined_Ieee_Math_Real_Realmax, + Iir_Predefined_Ieee_Math_Real_Realmin, + Iir_Predefined_Ieee_Math_Real_Sqrt, + Iir_Predefined_Ieee_Math_Real_Cbrt, + Iir_Predefined_Ieee_Math_Real_Pow_Int_Real, + Iir_Predefined_Ieee_Math_Real_Pow_Real_Real, + Iir_Predefined_Ieee_Math_Real_Exp, Iir_Predefined_Ieee_Math_Real_Log, Iir_Predefined_Ieee_Math_Real_Log2, Iir_Predefined_Ieee_Math_Real_Log10, + Iir_Predefined_Ieee_Math_Real_Log_Real_Real, Iir_Predefined_Ieee_Math_Real_Sin, Iir_Predefined_Ieee_Math_Real_Cos, + Iir_Predefined_Ieee_Math_Real_Tan, + Iir_Predefined_Ieee_Math_Real_Arcsin, + Iir_Predefined_Ieee_Math_Real_Arccos, Iir_Predefined_Ieee_Math_Real_Arctan, - Iir_Predefined_Ieee_Math_Real_Pow, + Iir_Predefined_Ieee_Math_Real_Arctan_Real_Real, + Iir_Predefined_Ieee_Math_Real_Sinh, + Iir_Predefined_Ieee_Math_Real_Cosh, + Iir_Predefined_Ieee_Math_Real_Tanh, + Iir_Predefined_Ieee_Math_Real_Arcsinh, + Iir_Predefined_Ieee_Math_Real_Arccosh, + Iir_Predefined_Ieee_Math_Real_Arctanh, -- Std_Logic_Unsigned (synopsys extension). Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, -- cgit v1.2.3