From 256bda5593e44bc2d95ebaf855ff00d4042f2a03 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 13 Oct 2022 03:05:42 +0200 Subject: synth-vhdl_stmts(synth_verification_unit): always set instance_pool. Fix #2214 --- src/synth/synth-vhdl_stmts.adb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index b64b6ec5a..ed2aeccb8 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -4770,10 +4770,12 @@ package body Synth.Vhdl_Stmts is Get_Sname (Syn_Inst)); Set_Extra (Syn_Inst, Parent_Inst, Unit_Sname); Mark (M, Proc_Pool); - Instance_Pool := Proc_Pool'Access; Item := Get_Vunit_Item_Chain (Unit); while Item /= Null_Node loop + -- Always set instance_pool. + -- (it is cleared by synth_concurrent_statement). + Instance_Pool := Proc_Pool'Access; case Get_Kind (Item) is when Iir_Kind_Psl_Default_Clock | Iir_Kind_Psl_Declaration -- cgit v1.2.3