From 1c18a124dc6749ef95c89012bf45ea1f2cdfa0d7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 11 Nov 2019 20:20:30 +0100
Subject: netlists-gates: add comments.

---
 src/synth/netlists-gates.ads | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src')

diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index f5b7e0492..b2a40fbf1 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -126,8 +126,11 @@ package Netlists.Gates is
 
    --  A simple DFF with an initial value (must be constant).  This is
    --  for FPGAs.
+   --  Input 0: Clock
+   --  Input 1: Data
    Id_Idff  : constant Module_Id := 52;
    --  A DFF with an asynchronous reset and an initial value.
+   --  Input 2: Initial value.
    Id_Iadff : constant Module_Id := 53;
 
    --  Width change: truncate or extend.  Sign is know in order to possibly
-- 
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