From a3f0fe3693602af086246ac57b0363578c96e171 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 10 Jan 2023 18:30:11 +0100 Subject: synth: add comments, minor rewrite --- src/vhdl/vhdl-sem_inst.adb | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/vhdl') diff --git a/src/vhdl/vhdl-sem_inst.adb b/src/vhdl/vhdl-sem_inst.adb index ba5c72acf..5394114a9 100644 --- a/src/vhdl/vhdl-sem_inst.adb +++ b/src/vhdl/vhdl-sem_inst.adb @@ -757,11 +757,12 @@ package body Vhdl.Sem_Inst is end if; when Iir_Kind_Interface_Type_Declaration => declare - Itype : Iir; + Def : Iir; begin - Itype := Instantiate_Iir (Get_Type (Inter), False); - Set_Type (Res, Itype); - Set_Interface_Type_Definition (Res, Itype); + -- Also instantiate the interface type definition. + Def := Instantiate_Iir (Get_Type (Inter), False); + Set_Type (Res, Def); + Set_Interface_Type_Definition (Res, Def); Set_Is_Ref (Res, True); end; when Iir_Kinds_Interface_Subprogram_Declaration => -- cgit v1.2.3