From a11d847187413ad04a6d98c1e867ccb5e385abe5 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 2 Jul 2019 19:02:56 +0200 Subject: synth: handle concurrent assertions. --- src/vhdl/vhdl-annotations.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/vhdl') diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index ace106d4f..2d02029ce 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1051,7 +1051,8 @@ package body Vhdl.Annotations is when Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment - | Iir_Kind_Concurrent_Conditional_Signal_Assignment => + | Iir_Kind_Concurrent_Conditional_Signal_Assignment + | Iir_Kind_Concurrent_Assertion_Statement => -- In case concurrent signal assignemnts were not -- canonicalized (for synthesis). null; -- cgit v1.2.3