From 7c8ed1216609d69cd6a092620d7aa1334e432fd9 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 16 Jul 2022 08:31:51 +0200 Subject: vhdl: preliminary work to elaborat quantities --- src/vhdl/vhdl-annotations.adb | 6 +++++- src/vhdl/vhdl-nodes_walk.adb | 1 + src/vhdl/vhdl-sem_decls.adb | 2 +- src/vhdl/vhdl-sem_names.adb | 2 ++ 4 files changed, 9 insertions(+), 2 deletions(-) (limited to 'src/vhdl') diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 8429d2dab..c36fec8ee 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -765,7 +765,8 @@ package body Vhdl.Annotations is when Iir_Kind_Terminal_Declaration => Add_Terminal_Info (Block_Info, Decl); - when Iir_Kinds_Branch_Quantity_Declaration => + when Iir_Kinds_Branch_Quantity_Declaration + | Iir_Kind_Free_Quantity_Declaration => Annotate_Declaration_Type (Block_Info, Decl); Add_Quantity_Info (Block_Info, Decl); @@ -1153,6 +1154,9 @@ package body Vhdl.Annotations is -- canonicalized (for synthesis). null; + when Iir_Kind_Concurrent_Break_Statement => + null; + when Iir_Kind_Concurrent_Procedure_Call_Statement => declare Info : Sim_Info_Acc; diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb index 442c105b7..bf4839d3b 100644 --- a/src/vhdl/vhdl-nodes_walk.adb +++ b/src/vhdl/vhdl-nodes_walk.adb @@ -157,6 +157,7 @@ package body Vhdl.Nodes_Walk is case Get_Kind (Stmt) is when Iir_Kinds_Simple_Concurrent_Statement | Iir_Kind_Component_Instantiation_Statement + | Iir_Kinds_Simultaneous_Statement | Iir_Kind_Psl_Default_Clock => Status := Cb.all (Stmt); when Iir_Kind_Block_Statement => diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 843b24123..6b3b1176a 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -69,7 +69,7 @@ package body Vhdl.Sem_Decls is Decl : Iir; begin -- We deal only with signal attribute. - pragma Assert (Get_Kind (Sig) in Iir_Kinds_Signal_Attribute); + pragma Assert (Get_Kind (Sig) in Iir_Kinds_AMS_Signal_Attribute); -- There must be a declarative part for implicit signals. pragma Assert (Current_Signals_Region.Decls_Parent /= Null_Iir); diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index bf195d91e..a7ec56888 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -1377,6 +1377,8 @@ package body Vhdl.Sem_Names is if Param /= Null_Iir then Set_Parameter (Attr, Param); end if; + + Sem_Decls.Add_Declaration_For_Implicit_Signal (Attr); end if; when Iir_Kind_Ramp_Attribute | Iir_Kind_Signal_Slew_Attribute -- cgit v1.2.3