From 698c668481e9ca77234317bca7047efd8210c24c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 29 Aug 2019 06:55:52 +0200
Subject: synth: add support for record types.

(WIP: need to fix regression of stmt01).
---
 src/vhdl/vhdl-annotations.adb | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/vhdl')

diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb
index 1e3b00043..d81e70adf 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -410,6 +410,10 @@ package body Vhdl.Annotations is
             end if;
 
          when Iir_Kind_Record_Type_Definition =>
+            if Flag_Synthesis then
+               --  For the offsets.
+               Create_Object_Info (Block_Info, Def, Kind_Type);
+            end if;
             declare
                List : constant Iir_Flist :=
                  Get_Elements_Declaration_List (Def);
-- 
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