From 664e84418a992b1a9d3977937ef1065970ed65ef Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 9 Mar 2020 18:30:36 +0100 Subject: synth: avoid crash on bad elaboration order. --- src/vhdl/vhdl-annotations.adb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/vhdl') diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index cf7659a22..aef7cafc0 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -741,7 +741,9 @@ package body Vhdl.Annotations is Annotate_Declaration_Type (Block_Info, Decl); Create_Signal_Info (Block_Info, Decl); when Iir_Kind_Anonymous_Signal_Declaration => - Create_Signal_Info (Block_Info, Decl); + if not Flag_Synthesis then + Create_Signal_Info (Block_Info, Decl); + end if; when Iir_Kind_Variable_Declaration | Iir_Kind_Iterator_Declaration => -- cgit v1.2.3