From 309014dcb97559210e561399757ccee01601a140 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Mar 2016 06:21:22 +0100
Subject: trans-chap12: extract gen_stubs from write_list_list.
---
src/vhdl/translate/trans-chap12.adb | 63 +++++++++++++++++++++++++++++--------
src/vhdl/translate/trans-chap12.ads | 4 +++
2 files changed, 54 insertions(+), 13 deletions(-)
(limited to 'src/vhdl/translate')
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 604f48e36..a5f2e9cfd 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -422,7 +422,7 @@ package body Trans.Chap12 is
end Gen_Dummy_Package_Declaration;
-- Write to file FILELIST all the files that are needed to link the design.
- procedure Write_File_List (Filelist : String)
+ procedure Gen_Stubs
is
use Interfaces.C_Streams;
use System;
@@ -505,6 +505,41 @@ package body Trans.Chap12 is
end loop;
end Add_File_Units;
+ File : Iir_Design_File;
+ Unit : Iir_Design_Unit;
+ J : Natural;
+ begin
+ -- Set elab flags on units, and remove it on design files.
+ for I in Design_Units.First .. Design_Units.Last loop
+ Unit := Design_Units.Table (I);
+ Set_Elab_Flag (Unit, True);
+ File := Get_Design_File (Unit);
+ Set_Elab_Flag (File, False);
+ end loop;
+
+ J := Design_Units.First;
+ while J <= Design_Units.Last loop
+ Unit := Design_Units.Table (J);
+ File := Get_Design_File (Unit);
+ if not Get_Elab_Flag (File) then
+ Set_Elab_Flag (File, True);
+
+ -- Add dependences of unused design units, otherwise the object
+ -- link case failed.
+ Add_File_Units (File);
+ end if;
+ J := J + 1;
+ end loop;
+ end Gen_Stubs;
+
+ -- Write to file FILELIST all the files that are needed to link the design.
+ procedure Write_File_List (Filelist : String)
+ is
+ use Interfaces.C_Streams;
+ use System;
+ use Configuration;
+ use Name_Table;
+
Nul : constant Character := Character'Val (0);
Fname : String := Filelist & Nul;
Mode : constant String := "wt" & Nul;
@@ -516,32 +551,25 @@ package body Trans.Chap12 is
Lib : Iir_Library_Declaration;
File : Iir_Design_File;
Unit : Iir_Design_Unit;
- J : Natural;
begin
F := fopen (Fname'Address, Mode'Address);
if F = NULL_Stream then
Error_Msg_Elab ("cannot open " & Filelist);
end if;
- -- Set elab flags on units, and remove it on design files.
+ -- Clear elab flags on design files.
for I in Design_Units.First .. Design_Units.Last loop
Unit := Design_Units.Table (I);
- Set_Elab_Flag (Unit, True);
File := Get_Design_File (Unit);
Set_Elab_Flag (File, False);
end loop;
- J := Design_Units.First;
- while J <= Design_Units.Last loop
+ for J in Design_Units.First .. Design_Units.Last loop
Unit := Design_Units.Table (J);
File := Get_Design_File (Unit);
if not Get_Elab_Flag (File) then
Set_Elab_Flag (File, True);
- -- Add dependences of unused design units, otherwise the object
- -- link case failed.
- Add_File_Units (File);
-
-- Write '>LIBRARY_DIRECTORY'.
Lib := Get_Library (File);
R := fputc (Character'Pos ('>'), F);
@@ -556,8 +584,9 @@ package body Trans.Chap12 is
size_t (Get_Name_Length (Id)), 1, F);
R := fputc (10, F);
end if;
- J := J + 1;
end loop;
+
+ R := fclose (F);
end Write_File_List;
procedure Elaborate (Primary : String;
@@ -702,12 +731,20 @@ package body Trans.Chap12 is
-- Index of the last design unit, required by the design.
Last_Design_Unit := Design_Units.Last;
- -- Disp list of files needed.
- -- FIXME: extract the link completion part of WRITE_FILE_LIST.
+ -- A design file may contain unused units that depends on other files.
+ -- In order to have all symbols resolved, also add unused packages and
+ -- generate stubs for referenced (but unused) entities and
+ -- configurations.
+ if not Whole then
+ Gen_Stubs;
+ end if;
+
+ -- Write the file containing the list of object files.
if Filelist /= "" then
Write_File_List (Filelist);
end if;
+ -- Disp list of files needed.
if Flags.Verbose then
Ada.Text_IO.Put_Line ("List of units not used:");
for I in Last_Design_Unit + 1 .. Design_Units.Last loop
diff --git a/src/vhdl/translate/trans-chap12.ads b/src/vhdl/translate/trans-chap12.ads
index 7e6231638..23abea998 100644
--- a/src/vhdl/translate/trans-chap12.ads
+++ b/src/vhdl/translate/trans-chap12.ads
@@ -20,8 +20,12 @@ package Trans.Chap12 is
-- Generate ortho declarations for elaboration.
procedure Gen_Elab_Decls;
+ -- Generate ortho code to elaborate declaration of the top unit.
procedure Call_Elab_Decls (Arch : Iir; Arch_Instance : O_Enode);
+ -- Write to file FILELIST all the files that are needed to link the design.
+ procedure Write_File_List (Filelist : String);
+
-- Primary unit + secondary unit (architecture name which may be null)
-- to elaborate.
procedure Elaborate (Primary : String;
--
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