From d8a81db96f512c0d58b554df294f4acb0915d6a9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 22 Jul 2020 06:57:46 +0200
Subject: vhdl: replace base_type with parent_type in nodes

Only for subtype definition and remove base_type in type definitions.
Allows to better track the addition of contraints.
---
 src/vhdl/simulate/simul-environments.adb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/vhdl/simulate')

diff --git a/src/vhdl/simulate/simul-environments.adb b/src/vhdl/simulate/simul-environments.adb
index 221e812d7..5e28441cf 100644
--- a/src/vhdl/simulate/simul-environments.adb
+++ b/src/vhdl/simulate/simul-environments.adb
@@ -22,6 +22,7 @@ with GNAT.Debug_Utilities;
 
 with Simple_IO;
 with Name_Table;
+with Vhdl.Utils; use Vhdl.Utils;
 with Simul.Debugger; use Simul.Debugger;
 
 package body Simul.Environments is
-- 
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