From d70084ccb149ff4f5fca072c672b1f3d040358a9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 11 Mar 2020 21:09:39 +0100
Subject: psl: keep denoting names in the PSL ast.

---
 src/vhdl/simulate/simul-simulation-main.adb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/vhdl/simulate')

diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index ae768b3d0..fcac44e3d 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -374,7 +374,8 @@ package body Simul.Simulation.Main is
       use PSL.Nodes;
    begin
       case Get_Kind (Expr) is
-         when N_HDL_Expr =>
+         when N_HDL_Expr
+           | N_HDL_Bool =>
             declare
                E : constant Iir := Get_HDL_Node (Expr);
                Rtype : constant Iir := Get_Base_Type (Get_Type (E));
-- 
cgit v1.2.3