From 9ef4ebe51b7290e363cedaf0c2cbf72ccef2443f Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 14 Dec 2018 19:14:03 +0100 Subject: files_map: renaming for consistency. --- src/vhdl/simulate/simul-debugger.adb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/vhdl/simulate') diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb index 4ddf1130c..6747179e8 100644 --- a/src/vhdl/simulate/simul-debugger.adb +++ b/src/vhdl/simulate/simul-debugger.adb @@ -1061,7 +1061,7 @@ package body Simul.Debugger is Line := 1; end if; - Pos := Line_To_Position (List_Current_File, Line); + Pos := File_Line_To_Position (List_Current_File, Line); Buf := Get_File_Source (List_Current_File); while Line < List_Current_Line + Radius loop @@ -1121,7 +1121,7 @@ package body Simul.Debugger is begin Location_To_Coord (Loc, File, Line_Pos, Line, Offset); Buf := Get_File_Source (File); - Next_Line_Pos := Line_To_Position (File, Line + 1); + Next_Line_Pos := File_Line_To_Position (File, Line + 1); Put (String (Buf (Line_Pos .. Next_Line_Pos - 1))); end Disp_Source_Line; -- cgit v1.2.3