From 61179df112a8a039dbf234eeb9dbfa7327a1f62c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 12 Jul 2019 19:42:48 +0200 Subject: simul-elaboration: rewrite assertion. --- src/vhdl/simulate/simul-elaboration.adb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/vhdl/simulate') diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index b4f690ab4..61048392b 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -2304,9 +2304,9 @@ package body Simul.Elaboration is El : Iir; Info : Sim_Info_Acc; begin - if List = Iir_Flist_All or else List = Iir_Flist_Others then - raise Internal_Error; - end if; + -- The list has been expanded by canon. + pragma Assert (List /= Iir_Flist_All + and then List /= Iir_Flist_Others); for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); Info := Get_Info (Get_Named_Entity (El)); -- cgit v1.2.3