From 2a21ee61dd73224bec023b3a541c9d4ddaee0f88 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 8 Jun 2019 06:49:26 +0200 Subject: synth: handle integer +/- for constants. --- src/vhdl/simulate/simul-annotations.adb | 3 ++- src/vhdl/simulate/simul-elaboration.adb | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/vhdl/simulate') diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index 8fb4c4fdc..f807f12b7 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -1021,7 +1021,8 @@ package body Simul.Annotations is null; when Iir_Kind_Concurrent_Simple_Signal_Assignment - | Iir_Kind_Concurrent_Selected_Signal_Assignment => + | Iir_Kind_Concurrent_Selected_Signal_Assignment + | Iir_Kind_Concurrent_Conditional_Signal_Assignment => -- In case concurrent signal assignemnts were not -- canonicalized (for synthesis). null; diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index f21c623eb..1638aa721 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1903,7 +1903,8 @@ package body Simul.Elaboration is Elaborate_Psl_Directive (Instance, Stmt); when Iir_Kind_Concurrent_Simple_Signal_Assignment - | Iir_Kind_Concurrent_Selected_Signal_Assignment => + | Iir_Kind_Concurrent_Selected_Signal_Assignment + | Iir_Kind_Concurrent_Conditional_Signal_Assignment => -- In case concurrent signal assignemnts were not -- canonicalized. null; -- cgit v1.2.3