From ec534f56b3dfe5b4dbfae63303bc0c23ce68d4eb Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 26 Dec 2022 09:18:35 +0100 Subject: simul: allow unassigned top generics --- src/synth/elab-vhdl_insts.adb | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/synth') diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index be7d5a7d5..389a816a4 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -910,11 +910,17 @@ package body Elab.Vhdl_Insts is Em : Mark_Type; Val : Valtyp; Inter_Typ : Type_Acc; + Defval : Node; begin Mark_Expr_Pool (Em); Inter_Typ := Elab_Declaration_Type (Top_Inst, Inter); - Val := Synth_Expression_With_Type - (Top_Inst, Get_Default_Value (Inter), Inter_Typ); + Defval := Get_Default_Value (Inter); + if Defval /= Null_Node then + Val := Synth_Expression_With_Type (Top_Inst, Defval, Inter_Typ); + else + -- Only for simulation, expect override. + Val := Create_Value_Default (Inter_Typ); + end if; pragma Assert (Is_Static (Val.Val)); Val := Unshare (Val, Instance_Pool); Val.Typ := Unshare_Type_Instance (Val.Typ, Inter_Typ); -- cgit v1.2.3