From db9c1fd3700995155b2d8a32d929b3d0dc9689e2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 12 Jun 2020 07:47:46 +0200 Subject: vhdl: analyze and synth concurrent statements in vunit. Fix #1366 --- src/synth/synth-stmts.adb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/synth') diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index a7b8dc232..cdc5290a4 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -3650,7 +3650,12 @@ package body Synth.Stmts is | Iir_Kind_Attribute_Declaration | Iir_Kind_Attribute_Specification => Synth_Declaration (Unit_Inst, Item, False, Last_Type); - when Iir_Kind_Concurrent_Simple_Signal_Assignment => + when Iir_Kinds_Concurrent_Signal_Assignment + | Iir_Kinds_Process_Statement + | Iir_Kinds_Generate_Statement + | Iir_Kind_Block_Statement + | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Component_Instantiation_Statement => Synth_Concurrent_Statement (Unit_Inst, Item); when others => Error_Kind ("synth_verification_unit", Item); -- cgit v1.2.3