From 3b0b2e79c310a0fff191036b3be5e15f9ae2e714 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 12 Jan 2020 02:31:50 +1100 Subject: netlists: Handle sdiv and udiv (#1082) --- src/synth/netlists-disp_vhdl.adb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/synth') diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 41c32eeaa..2348f669b 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -940,6 +940,12 @@ package body Netlists.Disp_Vhdl is when Id_Srem => Disp_Template (" \o0 <= std_logic_vector (\si0 rem \si1);" & NL, Inst); + when Id_Sdiv => + Disp_Template + (" \o0 <= std_logic_vector (\si0 / \si1);" & NL, Inst); + when Id_Udiv => + Disp_Template + (" \o0 <= std_logic_vector (\ui0 / \ui1);" & NL, Inst); when Id_Lsl => Disp_Template (" \o0 <= std_logic_vector " -- cgit v1.2.3