From 05ac81a5ff23ba45b5af45b29227f7cf5ed033fe Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 11 Sep 2019 06:46:39 +0200 Subject: synth: handle numeric_std.resize for signed. --- src/synth/synth-expr.adb | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/synth') diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 366e83d8e..d6651638f 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -2205,6 +2205,21 @@ package body Synth.Expr is (Synth_Uresize (Get_Net (V), W, Expr), Create_Vec_Type_By_Length (W, Logic_Type)); end; + when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat => + declare + V : constant Value_Acc := Subprg_Inst.Objects (1); + Sz : constant Value_Acc := Subprg_Inst.Objects (2); + W : Width; + begin + if not Is_Const (Sz) then + Error_Msg_Synth (+Expr, "size must be constant"); + return null; + end if; + W := Uns32 (Sz.Scal); + return Create_Value_Net + (Synth_Sresize (Get_Net (V), W, Expr), + Create_Vec_Type_By_Length (W, Logic_Type)); + end; when Iir_Predefined_Ieee_Math_Real_Log2 => declare V : constant Value_Acc := Subprg_Inst.Objects (1); -- cgit v1.2.3