From 99903b0932d000e92e2ed08d71c5354be0242093 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 19 Dec 2021 18:06:36 +0100 Subject: synth: add assertions --- src/synth/synth-vhdl_insts.adb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/synth/synth-vhdl_insts.adb') diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index 235d9ed8e..b02d2df69 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -121,6 +121,8 @@ package body Synth.Vhdl_Insts is end if; Inter := Get_Generic_Chain (Params.Decl); while Inter /= Null_Node loop + pragma Assert (Get_Kind (Inter) + = Iir_Kind_Interface_Constant_Declaration); if not Is_Equal (Get_Value (Obj.Syn_Inst, Inter), Get_Value (Params.Syn_Inst, Inter)) then @@ -131,6 +133,8 @@ package body Synth.Vhdl_Insts is Inter := Get_Port_Chain (Params.Decl); while Inter /= Null_Node loop + pragma Assert (Get_Kind (Inter) + = Iir_Kind_Interface_Signal_Declaration); if not Is_Fully_Constrained_Type (Get_Type (Inter)) then if not Are_Types_Equal (Get_Value (Obj.Syn_Inst, Inter).Typ, Get_Value (Params.Syn_Inst, Inter).Typ) -- cgit v1.2.3