From fe092cdc810cc559ed484f480d2072c43513a04a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 30 Sep 2022 06:53:59 +0200 Subject: synth: factorize code --- src/simul/simul-vhdl_simul.adb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 3eb3d2eed..0a07fc08b 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1034,6 +1034,14 @@ package body Simul.Vhdl_Simul is Ch := Synth_Expression (Inst, Get_Choice_Expression (Sw)); Eq := Is_Equal (Sel, Get_Memtyp (Ch)); end; + when Iir_Kind_Choice_By_Range => + declare + Bnd : Discrete_Range_Type; + begin + Elab.Vhdl_Types.Synth_Discrete_Range + (Inst, Get_Choice_Range (Sw), Bnd); + Eq := In_Range (Bnd, Read_Discrete (Sel)); + end; when Iir_Kind_Choice_By_Others => Eq := True; when others => -- cgit v1.2.3