From 9fb3ee1a53f26909a14090a7f7fc70bf149a670e Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 28 Apr 2021 21:23:59 +0200 Subject: ghdlsynth: never display a foreign module as pure vhdl (do not try to display the original entity when this is none) --- src/ghdldrv/ghdlsynth.adb | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/ghdldrv') diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 890be63ec..5d76355aa 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -439,8 +439,13 @@ package body Ghdlsynth is when Format_Dot => Netlists.Disp_Dot.Disp_Dot_Top_Module (Res); when Format_Vhdl => - Ent := Vhdl.Utils.Get_Entity_From_Configuration (Config); - Synth.Disp_Vhdl.Disp_Vhdl_Wrapper (Ent, Res, Inst); + if Get_Kind (Config) = Iir_Kind_Foreign_Module then + -- Not a VHDL design. + Netlists.Disp_Vhdl.Disp_Vhdl (Res); + else + Ent := Vhdl.Utils.Get_Entity_From_Configuration (Config); + Synth.Disp_Vhdl.Disp_Vhdl_Wrapper (Ent, Res, Inst); + end if; when Format_Raw_Vhdl => Netlists.Disp_Vhdl.Disp_Vhdl (Res); when Format_Verilog => -- cgit v1.2.3