From 6bc0f927f803debc51d5bb9bed46cf18b5a0435c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 28 Apr 2021 21:21:28 +0200
Subject: synth: add verilog output

---
 src/ghdldrv/ghdlsynth.adb | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/ghdldrv')

diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb
index 7a55cafee..890be63ec 100644
--- a/src/ghdldrv/ghdlsynth.adb
+++ b/src/ghdldrv/ghdlsynth.adb
@@ -43,6 +43,7 @@ with Vhdl.Utils;
 
 with Netlists.Dump;
 with Netlists.Disp_Vhdl;
+with Netlists.Disp_Verilog;
 with Netlists.Disp_Dot;
 with Netlists.Errors;
 
@@ -56,6 +57,7 @@ package body Ghdlsynth is
      (Format_Default,
       Format_Raw, Format_Dump, Format_Dot,
       Format_Vhdl, Format_Raw_Vhdl,
+      Format_Verilog,
       Format_None);
 
    type Name_Id_Array is array (Natural range <>) of Name_Id;
@@ -203,6 +205,8 @@ package body Ghdlsynth is
          Cmd.Oformat := Format_Vhdl;
       elsif Option = "--out=raw-vhdl" then
          Cmd.Oformat := Format_Raw_Vhdl;
+      elsif Option = "--out=verilog" then
+         Cmd.Oformat := Format_Verilog;
       elsif Option = "-di" then
          Flag_Debug_Noinference := True;
       elsif Option = "-dc" then
@@ -439,6 +443,8 @@ package body Ghdlsynth is
             Synth.Disp_Vhdl.Disp_Vhdl_Wrapper (Ent, Res, Inst);
          when Format_Raw_Vhdl =>
             Netlists.Disp_Vhdl.Disp_Vhdl (Res);
+         when Format_Verilog =>
+            Netlists.Disp_Verilog.Disp_Verilog (Res);
       end case;
    end Disp_Design;
 
-- 
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