From 2387eff54cb72997fb9afd30a2ea0754264deb3b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 19 Jun 2022 20:49:03 +0200 Subject: Enabled AMS support for all VHDL files. Added more [NOT IMPLEMENTED] rules to support VHDL-AMS code. --- pyGHDL/dom/NonStandard.py | 1 + pyGHDL/dom/_Translate.py | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) (limited to 'pyGHDL') diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index f6f451325..4e842f012 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -98,6 +98,7 @@ class Design(VHDLModel_Design): errorout_memory.Install_Handler() libghdl_set_option("--std=08") + libghdl_set_option("--ams") parse.Flag_Parse_Parenthesis.value = True diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index ee1586e6b..2f4a90343 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -823,6 +823,16 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str) -> print("[NOT IMPLEMENTED] Group template declaration in {name}".format(name=name)) elif kind == nodes.Iir_Kind.Disconnection_Specification: print("[NOT IMPLEMENTED] Disconnect specification in {name}".format(name=name)) + elif kind == nodes.Iir_Kind.Nature_Declaration: + print("[NOT IMPLEMENTED] Nature declaration in {name}".format(name=name)) + elif kind == nodes.Iir_Kind.Free_Quantity_Declaration: + print("[NOT IMPLEMENTED] Free quantity declaration in {name}".format(name=name)) + elif kind == nodes.Iir_Kind.Across_Quantity_Declaration: + print("[NOT IMPLEMENTED] Across quantity declaration in {name}".format(name=name)) + elif kind == nodes.Iir_Kind.Through_Quantity_Declaration: + print("[NOT IMPLEMENTED] Through quantity declaration in {name}".format(name=name)) + elif kind == nodes.Iir_Kind.Terminal_Declaration: + print("[NOT IMPLEMENTED] Terminal declaration in {name}".format(name=name)) else: position = Position.parse(item) raise DOMException( @@ -924,6 +934,12 @@ def GetConcurrentStatementsFromChainedNodes( yield ForGenerateStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Psl_Assert_Directive: yield ConcurrentAssertStatement.parse(statement, label) + elif kind == nodes.Iir_Kind.Simple_Simultaneous_Statement: + print( + "[NOT IMPLEMENTED] Simple simultaneous statement (label: '{label}') at line {line}".format( + label=label, line=pos.Line + ) + ) else: raise DOMException( "Unknown statement of kind '{kind}' in {entity} '{name}' at {file}:{line}:{column}.".format( -- cgit v1.2.3