From d9241cf7156ff2e8b1ce8258e780eb9c8bf1e38f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 20 Jun 2021 16:52:45 +0200 Subject: Added concatenation and string literal. --- pyGHDL/dom/Expression.py | 31 ++++++++++++++++--------------- pyGHDL/dom/Literal.py | 10 ++++++++++ pyGHDL/dom/_Translate.py | 28 ++++++++++++++++------------ 3 files changed, 42 insertions(+), 27 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index fec347b57..75d288a83 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -32,19 +32,6 @@ # ============================================================================ from typing import List -from pyGHDL.dom.Aggregates import ( - OthersAggregateElement, - SimpleAggregateElement, - RangedAggregateElement, - IndexedAggregateElement, - NamedAggregateElement, -) -from pyGHDL.dom.Symbol import EnumerationLiteralSymbol -from pyGHDL.libghdl import utils - -from pyGHDL.dom.Common import DOMException -from pyGHDL.dom._Utils import GetIirKindOfNode -from pyGHDL.libghdl.vhdl import nodes from pydecor import export from pyVHDLModel.VHDLModel import ( @@ -86,6 +73,20 @@ from pyVHDLModel.VHDLModel import ( AggregateElement, ) +from pyGHDL.libghdl import utils +from pyGHDL.libghdl.vhdl import nodes +from pyGHDL.dom._Utils import GetIirKindOfNode +from pyGHDL.dom.Common import DOMException +from pyGHDL.dom.Symbol import EnumerationLiteralSymbol +from pyGHDL.dom.Aggregates import ( + OthersAggregateElement, + SimpleAggregateElement, + RangedAggregateElement, + IndexedAggregateElement, + NamedAggregateElement, +) + + __all__ = [] @@ -391,7 +392,7 @@ class Aggregate(VHDLModel_Aggregate): @classmethod def parse(cls, node): - from pyGHDL.dom._Translate import GetExpressionFromNode + from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode choices = [] @@ -406,7 +407,7 @@ class Aggregate(VHDLModel_Aggregate): value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) choices.append(IndexedAggregateElement(index, value)) elif kind == nodes.Iir_Kind.Choice_By_Range: - r = GetExpressionFromNode(nodes.Get_Choice_Range(item)) + r = GetRangeFromNode(nodes.Get_Choice_Range(item)) value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) choices.append(RangedAggregateElement(r, value)) elif kind == nodes.Iir_Kind.Choice_By_Name: diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 7c722583b..334355b35 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -39,6 +39,7 @@ from pyVHDLModel.VHDLModel import ( IntegerLiteral as VHDLModel_IntegerLiteral, FloatingPointLiteral as VHDLModel_FloatingPointLiteral, CharacterLiteral as VHDLModel_CharacterLiteral, + StringLiteral as VHDLModel_StringLiteral, ) __all__ = [] @@ -67,3 +68,12 @@ class CharacterLiteral(VHDLModel_CharacterLiteral): identifier = nodes.Get_Identifier(node) value = name_table.Get_Character(identifier) return cls(value) + + +@export +class StringLiteral(VHDLModel_StringLiteral): + @classmethod + def parse(cls, node): + stringID = nodes.Get_String8_Id(node) + value = name_table.Get_Name_Ptr(stringID) + return cls(value) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 24f056f33..a18f738df 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -46,7 +46,7 @@ from pyGHDL.dom.Symbol import ( SimpleSubTypeSymbol, ConstrainedSubTypeSymbol, ) -from pyGHDL.dom.Literal import IntegerLiteral, CharacterLiteral, FloatingPointLiteral +from pyGHDL.dom.Literal import IntegerLiteral, CharacterLiteral, FloatingPointLiteral, StringLiteral from pyGHDL.dom.Expression import ( SubtractionExpression, AdditionExpression, @@ -56,7 +56,7 @@ from pyGHDL.dom.Expression import ( ExponentiationExpression, Aggregate, NegationExpression, - ParenthesisExpression, + ParenthesisExpression, ConcatenationExpression, ) __all__ = [] @@ -101,16 +101,7 @@ def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constrai for constraint in flist_iter(nodes.Get_Index_Constraint_List(subTypeIndication)): constraintKind = GetIirKindOfNode(constraint) if constraintKind == nodes.Iir_Kind.Range_Expression: - direction = nodes.Get_Direction(constraint) - leftBound = nodes.Get_Left_Limit_Expr(constraint) - rightBound = nodes.Get_Right_Limit_Expr(constraint) - - r = Range( - GetExpressionFromNode(leftBound), - GetExpressionFromNode(rightBound), - Direction.DownTo if direction else Direction.To, - ) - constraints.append(RangeExpression(r)) + constraints.append(RangeExpression(GetRangeFromNode(constraint))) elif constraintKind == nodes.Iir_Kind.Attribute_Name: raise DOMException("[NOT IMPLEMENTED] Attribute name as range.") elif constraintKind == nodes.Iir_Kind.Simple_Name: @@ -132,8 +123,10 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Integer_Literal: IntegerLiteral, nodes.Iir_Kind.Floating_Point_Literal: FloatingPointLiteral, nodes.Iir_Kind.Character_Literal: CharacterLiteral, + nodes.Iir_Kind.String_Literal8: StringLiteral, nodes.Iir_Kind.Negation_Operator: NegationExpression, nodes.Iir_Kind.Addition_Operator: AdditionExpression, + nodes.Iir_Kind.Concatenation_Operator: ConcatenationExpression, nodes.Iir_Kind.Not_Operator: InverseExpression, nodes.Iir_Kind.Parenthesis_Expression: ParenthesisExpression, nodes.Iir_Kind.Substraction_Operator: SubtractionExpression, @@ -143,6 +136,17 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Aggregate: Aggregate, } +@export +def GetRangeFromNode(node) -> Range: + direction = nodes.Get_Direction(node) + leftBound = nodes.Get_Left_Limit_Expr(node) + rightBound = nodes.Get_Right_Limit_Expr(node) + + return Range( + GetExpressionFromNode(leftBound), + GetExpressionFromNode(rightBound), + Direction.DownTo if direction else Direction.To, + ) @export def GetExpressionFromNode(node) -> Expression: -- cgit v1.2.3 From ee253532230b5c1904844006e2a4bd8ec8cffc1d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 20 Jun 2021 17:23:21 +0200 Subject: Handle OthersAggregateElement properly. --- pyGHDL/dom/Expression.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 75d288a83..d55ea8cef 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -399,24 +399,21 @@ class Aggregate(VHDLModel_Aggregate): choicesChain = nodes.Get_Association_Choices_Chain(node) for item in utils.chain_iter(choicesChain): kind = GetIirKindOfNode(item) + value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) + if kind == nodes.Iir_Kind.Choice_By_None: - value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) choices.append(SimpleAggregateElement(value)) elif kind == nodes.Iir_Kind.Choice_By_Expression: index = GetExpressionFromNode(nodes.Get_Choice_Expression(item)) - value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) choices.append(IndexedAggregateElement(index, value)) elif kind == nodes.Iir_Kind.Choice_By_Range: r = GetRangeFromNode(nodes.Get_Choice_Range(item)) - value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) choices.append(RangedAggregateElement(r, value)) elif kind == nodes.Iir_Kind.Choice_By_Name: name = EnumerationLiteralSymbol(nodes.Get_Choice_Name(item)) - value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) choices.append(NamedAggregateElement(name, value)) elif kind == nodes.Iir_Kind.Choice_By_Others: - expression = None - choices.append(OthersAggregateElement(expression)) + choices.append(OthersAggregateElement(value)) else: raise DOMException( "Unknown choice kind '{kindName}'({kind}) in aggregate '{aggr}'.".format( -- cgit v1.2.3 From e41f119ea07c83842599fdd4ff1dd8e235eb791e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 14:32:57 +0200 Subject: Handle more expressions (logical, compare, rem/mod). --- pyGHDL/dom/Expression.py | 40 +++++++++++++++++++++++++++++++------- pyGHDL/dom/_Translate.py | 50 ++++++++++++++++++++++++++++++++++++------------ 2 files changed, 71 insertions(+), 19 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index d55ea8cef..30684394b 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -39,7 +39,7 @@ from pyVHDLModel.VHDLModel import ( IdentityExpression as VHDLModel_IdentityExpression, NegationExpression as VHDLModel_NegationExpression, AbsoluteExpression as VHDLModel_AbsoluteExpression, - ParenthesisExpression as VHDLModel_ParenthesisExpression, + SubExpression as VHDLModel_ParenthesisExpression, TypeConversion as VHDLModel_TypeConversion, FunctionCall as VHDLModel_FunctionCall, QualifiedExpression as VHDLModel_QualifiedExpression, @@ -59,9 +59,10 @@ from pyVHDLModel.VHDLModel import ( XnorExpression as VHDLModel_XnorExpression, EqualExpression as VHDLModel_EqualExpression, UnequalExpression as VHDLModel_UnequalExpression, + LessThanExpression as VHDLModel_LessThanExpression, + LessEqualExpression as VHDLModel_LessEqualExpression, GreaterThanExpression as VHDLModel_GreaterThanExpression, GreaterEqualExpression as VHDLModel_GreaterEqualExpression, - LessThanExpression as VHDLModel_LessThanExpression, ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, @@ -70,14 +71,14 @@ from pyVHDLModel.VHDLModel import ( RotateLeftExpression as VHDLModel_RotateLeftExpression, Aggregate as VHDLModel_Aggregate, Expression, - AggregateElement, + AggregateElement, SubTypeOrSymbol, ) from pyGHDL.libghdl import utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom.Common import DOMException -from pyGHDL.dom.Symbol import EnumerationLiteralSymbol +from pyGHDL.dom.Symbol import EnumerationLiteralSymbol, SimpleSubTypeSymbol from pyGHDL.dom.Aggregates import ( OthersAggregateElement, SimpleAggregateElement, @@ -305,7 +306,7 @@ class UnequalExpression(VHDLModel_UnequalExpression, _ParseBinaryExpression): @export -class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpression): +class LessThanExpression(VHDLModel_LessThanExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -313,7 +314,7 @@ class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpress @export -class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpression): +class LessEqualExpression(VHDLModel_LessEqualExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -321,7 +322,15 @@ class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpre @export -class LessThanExpression(VHDLModel_LessThanExpression, _ParseBinaryExpression): +class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpression): + def __init__(self, left: Expression, right: Expression): + super().__init__() + self._leftOperand = left + self._rightOperand = right + + +@export +class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -384,6 +393,23 @@ class RotateLeftExpression(VHDLModel_RotateLeftExpression, _ParseBinaryExpressio self._rightOperand = right +@export +class QualifiedExpression(VHDLModel_QualifiedExpression): + def __init__(self, subType: SubTypeOrSymbol, operand: Expression): + super().__init__() + self._subtype = subType + self._operand = operand + + @classmethod + def parse(cls, node): + from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode + + typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) + subType = SimpleSubTypeSymbol(typeMarkName) + operand = GetExpressionFromNode(nodes.Get_Expression(node)) + return cls(subType, operand) + + @export class Aggregate(VHDLModel_Aggregate): def __init__(self, elements: List[AggregateElement]): diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index a18f738df..2445d0574 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -56,7 +56,10 @@ from pyGHDL.dom.Expression import ( ExponentiationExpression, Aggregate, NegationExpression, - ParenthesisExpression, ConcatenationExpression, + ParenthesisExpression, ConcatenationExpression, QualifiedExpression, ModuloExpression, RemainderExpression, AndExpression, NandExpression, OrExpression, + NorExpression, XorExpression, XnorExpression, EqualExpression, UnequalExpression, LessThanExpression, GreaterThanExpression, GreaterEqualExpression, + LessEqualExpression, ShiftLeftLogicExpression, ShiftRightLogicExpression, ShiftLeftArithmeticExpression, ShiftRightArithmeticExpression, + RotateLeftExpression, RotateRightExpression, ) __all__ = [] @@ -118,6 +121,19 @@ def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constrai return constraints +@export +def GetRangeFromNode(node) -> Range: + direction = nodes.Get_Direction(node) + leftBound = nodes.Get_Left_Limit_Expr(node) + rightBound = nodes.Get_Right_Limit_Expr(node) + + return Range( + GetExpressionFromNode(leftBound), + GetExpressionFromNode(rightBound), + Direction.DownTo if direction else Direction.To, + ) + + __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Simple_Name: SimpleObjectSymbol, nodes.Iir_Kind.Integer_Literal: IntegerLiteral, @@ -132,21 +148,31 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Substraction_Operator: SubtractionExpression, nodes.Iir_Kind.Multiplication_Operator: MultiplyExpression, nodes.Iir_Kind.Division_Operator: DivisionExpression, + nodes.Iir_Kind.Modulus_Operator: ModuloExpression, + nodes.Iir_Kind.Remainder_Operator: RemainderExpression, nodes.Iir_Kind.Exponentiation_Operator: ExponentiationExpression, + nodes.Iir_Kind.And_Operator: AndExpression, + nodes.Iir_Kind.Nand_Operator: NandExpression, + nodes.Iir_Kind.Or_Operator: OrExpression, + nodes.Iir_Kind.Nor_Operator: NorExpression, + nodes.Iir_Kind.Xor_Operator: XorExpression, + nodes.Iir_Kind.Xnor_Operator: XnorExpression, + nodes.Iir_Kind.Equality_Operator: EqualExpression, + nodes.Iir_Kind.Inequality_Operator: UnequalExpression, + nodes.Iir_Kind.Less_Than_Operator: LessThanExpression, + nodes.Iir_Kind.Less_Than_Or_Equal_Operator: LessEqualExpression, + nodes.Iir_Kind.Greater_Than_Operator: GreaterThanExpression, + nodes.Iir_Kind.Greater_Than_Or_Equal_Operator: GreaterEqualExpression, + nodes.Iir_Kind.Sll_Operator: ShiftLeftLogicExpression, + nodes.Iir_Kind.Srl_Operator: ShiftRightLogicExpression, + nodes.Iir_Kind.Sla_Operator: ShiftLeftArithmeticExpression, + nodes.Iir_Kind.Sra_Operator: ShiftRightArithmeticExpression, + nodes.Iir_Kind.Rol_Operator: RotateLeftExpression, + nodes.Iir_Kind.Ror_Operator: RotateRightExpression, + nodes.Iir_Kind.Qualified_Expression: QualifiedExpression, nodes.Iir_Kind.Aggregate: Aggregate, } -@export -def GetRangeFromNode(node) -> Range: - direction = nodes.Get_Direction(node) - leftBound = nodes.Get_Left_Limit_Expr(node) - rightBound = nodes.Get_Right_Limit_Expr(node) - - return Range( - GetExpressionFromNode(leftBound), - GetExpressionFromNode(rightBound), - Direction.DownTo if direction else Direction.To, - ) @export def GetExpressionFromNode(node) -> Expression: -- cgit v1.2.3 From 5303bb777dedfa03bbc3d042bb14c5d9bbae6b52 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 14:34:03 +0200 Subject: Renamed 'NodeToName' to 'GetNameOfNode'. --- pyGHDL/dom/DesignUnit.py | 16 ++++++++-------- pyGHDL/dom/InterfaceItem.py | 6 +++--- pyGHDL/dom/Object.py | 8 ++++---- pyGHDL/dom/Symbol.py | 2 +- pyGHDL/dom/_Translate.py | 14 +++++++------- pyGHDL/dom/_Utils.py | 2 +- 6 files changed, 24 insertions(+), 24 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 534149677..8e10aa815 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -51,7 +51,7 @@ from pyVHDLModel.VHDLModel import Configuration as VHDLModel_Configuration from pyGHDL.libghdl.vhdl import nodes -from pyGHDL.dom._Utils import NodeToName +from pyGHDL.dom._Utils import GetNameOfNode from pyGHDL.dom._Translate import ( GetGenericsFromChainedNodes, GetPortsFromChainedNodes, @@ -67,7 +67,7 @@ __all__ = [] class Entity(VHDLModel_Entity, GHDLMixin): @classmethod def parse(cls, libraryUnit): - name = NodeToName(libraryUnit) + name = GetNameOfNode(libraryUnit) entity = cls(name) for generic in GetGenericsFromChainedNodes( @@ -95,8 +95,8 @@ class Architecture(VHDLModel_Architecture, GHDLMixin): @classmethod def parse(cls, libraryUnit): - name = NodeToName(libraryUnit) - entityName = NodeToName(nodes.Get_Entity_Name(libraryUnit)) + name = GetNameOfNode(libraryUnit) + entityName = GetNameOfNode(nodes.Get_Entity_Name(libraryUnit)) entity = EntitySymbol(entityName) architecture = cls(name, entity) @@ -116,7 +116,7 @@ class Architecture(VHDLModel_Architecture, GHDLMixin): class Package(VHDLModel_Package, GHDLMixin): @classmethod def parse(cls, libraryUnit): - name = NodeToName(libraryUnit) + name = GetNameOfNode(libraryUnit) package = cls(name) @@ -132,7 +132,7 @@ class Package(VHDLModel_Package, GHDLMixin): class PackageBody(VHDLModel_PackageBody, GHDLMixin): @classmethod def parse(cls, libraryUnit): - name = NodeToName(libraryUnit) + name = GetNameOfNode(libraryUnit) packageBody = cls(name) @@ -148,7 +148,7 @@ class PackageBody(VHDLModel_PackageBody, GHDLMixin): class Context(VHDLModel_Context, GHDLMixin): @classmethod def parse(cls, libraryUnit): - name = NodeToName(libraryUnit) + name = GetNameOfNode(libraryUnit) return cls(name) @@ -156,5 +156,5 @@ class Context(VHDLModel_Context, GHDLMixin): class Configuration(VHDLModel_Configuration, GHDLMixin): @classmethod def parse(cls, libraryUnit): - name = NodeToName(libraryUnit) + name = GetNameOfNode(libraryUnit) return cls(name) diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index c2cd3a2c9..6c0d2641b 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -43,7 +43,7 @@ from pyVHDLModel.VHDLModel import ( Expression, ) -from pyGHDL.dom._Utils import NodeToName, GetModeOfNode +from pyGHDL.dom._Utils import GetNameOfNode, GetModeOfNode from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode from pyGHDL.dom.Common import GHDLMixin @@ -54,7 +54,7 @@ __all__ = [] class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLMixin): @classmethod def parse(cls, generic): - name = NodeToName(generic) + name = GetNameOfNode(generic) mode = GetModeOfNode(generic) subTypeIndication = GetSubtypeIndicationFromNode(generic, "generic", name) default = nodes.Get_Default_Value(generic) @@ -80,7 +80,7 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLM class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin): @classmethod def parse(cls, port): - name = NodeToName(port) + name = GetNameOfNode(port) mode = GetModeOfNode(port) subTypeIndication = GetSubtypeIndicationFromNode(port, "port", name) diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py index bd37455ea..1f1f8f6d9 100644 --- a/pyGHDL/dom/Object.py +++ b/pyGHDL/dom/Object.py @@ -34,7 +34,7 @@ from pyGHDL.libghdl.vhdl import nodes from pydecor import export from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode -from pyGHDL.dom._Utils import NodeToName +from pyGHDL.dom._Utils import GetNameOfNode from pyVHDLModel.VHDLModel import ( Constant as VHDLModel_Constant, Variable as VHDLModel_Variable, @@ -59,7 +59,7 @@ class Constant(VHDLModel_Constant): @classmethod def parse(cls, node): - name = NodeToName(node) + name = GetNameOfNode(node) subTypeIndication = GetSubtypeIndicationFromNode(node, "constant", name) defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(node)) @@ -81,7 +81,7 @@ class Variable(VHDLModel_Variable): @classmethod def parse(cls, node): - name = NodeToName(node) + name = GetNameOfNode(node) subTypeIndication = GetSubtypeIndicationFromNode(node, "variable", name) defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(node)) @@ -103,7 +103,7 @@ class Signal(VHDLModel_Signal): @classmethod def parse(cls, node): - name = NodeToName(node) + name = GetNameOfNode(node) subTypeIndication = GetSubtypeIndicationFromNode(node, "signal", name) default = nodes.Get_Default_Value(node) defaultExpression = GetExpressionFromNode(default) if default else None diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 020f9fbc7..af9e59b1d 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -34,7 +34,7 @@ from pydecor import export from typing import List -from pyGHDL.dom._Utils import NodeToName +from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode from pyVHDLModel.VHDLModel import ( EntitySymbol as VHDLModel_EntitySymbol, SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 2445d0574..119f5816e 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -38,7 +38,7 @@ from pyVHDLModel.VHDLModel import Constraint, Direction, Expression, SubTypeOrSy from pyGHDL.libghdl import utils from pyGHDL.libghdl.utils import flist_iter from pyGHDL.libghdl.vhdl import nodes -from pyGHDL.dom._Utils import NodeToName, GetIirKindOfNode +from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode from pyGHDL.dom.Common import DOMException from pyGHDL.dom.Range import Range, RangeExpression from pyGHDL.dom.Symbol import ( @@ -73,12 +73,12 @@ def GetSubtypeIndicationFromNode(node, entity: str, name: str) -> SubTypeOrSymbo subTypeKind = GetIirKindOfNode(subTypeIndication) if subTypeKind == nodes.Iir_Kind.Simple_Name: - subTypeName = NodeToName(subTypeIndication) + subTypeName = GetNameOfNode(subTypeIndication) subType = SimpleSubTypeSymbol(subTypeName) elif subTypeKind == nodes.Iir_Kind.Array_Subtype_Definition: typeMark = nodes.Get_Subtype_Type_Mark(subTypeIndication) - typeMarkName = NodeToName(typeMark) + typeMarkName = GetNameOfNode(typeMark) constraints = GetArrayConstraintsFromSubtypeIndication(subTypeIndication) subType = ConstrainedSubTypeSymbol(typeMarkName, constraints) @@ -247,19 +247,19 @@ def GetDeclaredItemsFromChainedNodes(nodeChain, entity: str, name: str): result.append(Signal.parse(item)) elif kind == nodes.Iir_Kind.Anonymous_Type_Declaration: - typeName = NodeToName(item) + typeName = GetNameOfNode(item) print("found type '{name}'".format(name=typeName)) elif kind == nodes.Iir_Kind.Subtype_Declaration: - subTypeName = NodeToName(item) + subTypeName = GetNameOfNode(item) print("found subtype '{name}'".format(name=subTypeName)) elif kind == nodes.Iir_Kind.Function_Declaration: - functionName = NodeToName(item) + functionName = GetNameOfNode(item) print("found function '{name}'".format(name=functionName)) elif kind == nodes.Iir_Kind.Function_Body: # functionName = NodeToName(item) print("found function body '{name}'".format(name="????")) elif kind == nodes.Iir_Kind.Object_Alias_Declaration: - aliasName = NodeToName(item) + aliasName = GetNameOfNode(item) print("found alias '{name}'".format(name=aliasName)) else: raise DOMException( diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index dbbb69e81..b5cf1fc5c 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -56,7 +56,7 @@ def GetIirKindOfNode(node) -> nodes.Iir_Kind: @export -def NodeToName(node) -> str: +def GetNameOfNode(node) -> str: """Return the python string from node :obj:`node` identifier""" identifier = nodes.Get_Identifier(node) return name_table.Get_Name_Ptr(identifier) -- cgit v1.2.3 From f0796bfab0032e6e7f9c8f52b789bab06ab7e4df Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 14:34:42 +0200 Subject: Start handling function calls. --- pyGHDL/dom/Symbol.py | 33 ++++++++++++++++++++++++++++++--- pyGHDL/dom/_Translate.py | 7 ++++--- 2 files changed, 34 insertions(+), 6 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index af9e59b1d..c82c39729 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -30,6 +30,10 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from pyGHDL.dom.Common import DOMException +from pyGHDL.libghdl import utils + +from pyGHDL.libghdl.vhdl import nodes from pydecor import export from typing import List @@ -40,7 +44,8 @@ from pyVHDLModel.VHDLModel import ( SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, ConstrainedSubTypeSymbol as VHDLModel_ConstrainedSubTypeSymbol, EnumerationLiteralSymbol as VHDLModel_EnumerationLiteralSymbol, - SimpleObjectSymbol as VHDLModel_SimpleObjectSymbol, + SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol, + IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol, Constraint, ) @@ -80,8 +85,30 @@ class ConstrainedSubTypeSymbol(VHDLModel_ConstrainedSubTypeSymbol): @export -class SimpleObjectSymbol(VHDLModel_SimpleObjectSymbol): +class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbol): + @classmethod + def parse(cls, node): + name = GetNameOfNode(node) + return cls(name) + + +@export +class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSymbol): @classmethod def parse(cls, node): - name = NodeToName(node) + prefix = nodes.Get_Prefix(node) + name = GetNameOfNode(prefix) + + for item in utils.chain_iter(nodes.Get_Association_Chain(node)): + kind = GetIirKindOfNode(item) + + if kind == nodes.Iir_Kind.Association_Element_By_Expression: + pass + else: + raise DOMException( + "Unknown association kind '{kindName}'({kind}) in array index or function call '{node}'.".format( + kind=kind, kindName=kind.name, node=node + ) + ) + return cls(name) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 119f5816e..eed6a226b 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -42,9 +42,9 @@ from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode from pyGHDL.dom.Common import DOMException from pyGHDL.dom.Range import Range, RangeExpression from pyGHDL.dom.Symbol import ( - SimpleObjectSymbol, + SimpleObjectOrFunctionCallSymbol, SimpleSubTypeSymbol, - ConstrainedSubTypeSymbol, + ConstrainedSubTypeSymbol, IndexedObjectOrFunctionCallSymbol, ) from pyGHDL.dom.Literal import IntegerLiteral, CharacterLiteral, FloatingPointLiteral, StringLiteral from pyGHDL.dom.Expression import ( @@ -135,7 +135,8 @@ def GetRangeFromNode(node) -> Range: __EXPRESSION_TRANSLATION = { - nodes.Iir_Kind.Simple_Name: SimpleObjectSymbol, + nodes.Iir_Kind.Simple_Name: SimpleObjectOrFunctionCallSymbol, + nodes.Iir_Kind.Parenthesis_Name: IndexedObjectOrFunctionCallSymbol, nodes.Iir_Kind.Integer_Literal: IntegerLiteral, nodes.Iir_Kind.Floating_Point_Literal: FloatingPointLiteral, nodes.Iir_Kind.Character_Literal: CharacterLiteral, -- cgit v1.2.3 From 19ba3d3e37b02e870ed6c6e283c267d904cafac8 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 14:35:30 +0200 Subject: Asked black for his opinion. --- pyGHDL/dom/Expression.py | 3 ++- pyGHDL/dom/_Translate.py | 37 +++++++++++++++++++++++++++++++------ 2 files changed, 33 insertions(+), 7 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 30684394b..2802351d4 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -71,7 +71,8 @@ from pyVHDLModel.VHDLModel import ( RotateLeftExpression as VHDLModel_RotateLeftExpression, Aggregate as VHDLModel_Aggregate, Expression, - AggregateElement, SubTypeOrSymbol, + AggregateElement, + SubTypeOrSymbol, ) from pyGHDL.libghdl import utils diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index eed6a226b..af6e5420f 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -44,9 +44,15 @@ from pyGHDL.dom.Range import Range, RangeExpression from pyGHDL.dom.Symbol import ( SimpleObjectOrFunctionCallSymbol, SimpleSubTypeSymbol, - ConstrainedSubTypeSymbol, IndexedObjectOrFunctionCallSymbol, + ConstrainedSubTypeSymbol, + IndexedObjectOrFunctionCallSymbol, +) +from pyGHDL.dom.Literal import ( + IntegerLiteral, + CharacterLiteral, + FloatingPointLiteral, + StringLiteral, ) -from pyGHDL.dom.Literal import IntegerLiteral, CharacterLiteral, FloatingPointLiteral, StringLiteral from pyGHDL.dom.Expression import ( SubtractionExpression, AdditionExpression, @@ -56,10 +62,29 @@ from pyGHDL.dom.Expression import ( ExponentiationExpression, Aggregate, NegationExpression, - ParenthesisExpression, ConcatenationExpression, QualifiedExpression, ModuloExpression, RemainderExpression, AndExpression, NandExpression, OrExpression, - NorExpression, XorExpression, XnorExpression, EqualExpression, UnequalExpression, LessThanExpression, GreaterThanExpression, GreaterEqualExpression, - LessEqualExpression, ShiftLeftLogicExpression, ShiftRightLogicExpression, ShiftLeftArithmeticExpression, ShiftRightArithmeticExpression, - RotateLeftExpression, RotateRightExpression, + ParenthesisExpression, + ConcatenationExpression, + QualifiedExpression, + ModuloExpression, + RemainderExpression, + AndExpression, + NandExpression, + OrExpression, + NorExpression, + XorExpression, + XnorExpression, + EqualExpression, + UnequalExpression, + LessThanExpression, + GreaterThanExpression, + GreaterEqualExpression, + LessEqualExpression, + ShiftLeftLogicExpression, + ShiftRightLogicExpression, + ShiftLeftArithmeticExpression, + ShiftRightArithmeticExpression, + RotateLeftExpression, + RotateRightExpression, ) __all__ = [] -- cgit v1.2.3 From ec37f2b5efe56d442ea51d3e10d16742f3cd4bce Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 15:21:06 +0200 Subject: Minimal handling of types and subtypes. --- pyGHDL/dom/Symbol.py | 27 ++++++++++++-------- pyGHDL/dom/Type.py | 21 ++++++++++++++++ pyGHDL/dom/_Translate.py | 49 +++++++++++++++++++++++++++--------- pyGHDL/dom/formatting/prettyprint.py | 18 +++++++++++++ 4 files changed, 93 insertions(+), 22 deletions(-) create mode 100644 pyGHDL/dom/Type.py (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index c82c39729..047fd624f 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -30,15 +30,9 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ -from pyGHDL.dom.Common import DOMException -from pyGHDL.libghdl import utils - -from pyGHDL.libghdl.vhdl import nodes -from pydecor import export - from typing import List +from pydecor import export -from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode from pyVHDLModel.VHDLModel import ( EntitySymbol as VHDLModel_EntitySymbol, SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, @@ -49,6 +43,11 @@ from pyVHDLModel.VHDLModel import ( Constraint, ) +from pyGHDL.libghdl import utils +from pyGHDL.libghdl.vhdl import nodes +from pyGHDL.dom._Utils import GetIirKindOfNode, GetNameOfNode +from pyGHDL.dom.Common import DOMException + __all__ = [] @@ -94,21 +93,29 @@ class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbo @export class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSymbol): + def __init__(self, name: str, associations: List): + super().__init__(objectName=name) + @classmethod def parse(cls, node): + from pyGHDL.dom._Translate import GetExpressionFromNode + prefix = nodes.Get_Prefix(node) name = GetNameOfNode(prefix) + associations = [] for item in utils.chain_iter(nodes.Get_Association_Chain(node)): kind = GetIirKindOfNode(item) if kind == nodes.Iir_Kind.Association_Element_By_Expression: - pass + expr = None # GetExpressionFromNode(nodes.Get_Associated_Expr(item)) + + associations.append(expr) else: raise DOMException( - "Unknown association kind '{kindName}'({kind}) in array index or function call '{node}'.".format( + "Unknown association kind '{kindName}'({kind}) in array index/slice or function call '{node}'.".format( kind=kind, kindName=kind.name, node=node ) ) - return cls(name) + return cls(name, associations) diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py new file mode 100644 index 000000000..df143b4d0 --- /dev/null +++ b/pyGHDL/dom/Type.py @@ -0,0 +1,21 @@ +from pydecor import export + +from pyVHDLModel.VHDLModel import ( + IntegerType as VHDLModel_IntegerType, + SubType as VHDLModel_SubType, + Expression, +) + + +@export +class IntegerType(VHDLModel_IntegerType): + def __init__(self, typeName: str, leftBound: Expression, rightBound: Expression): + super().__init__(typeName) + self._leftBound = leftBound + self._rightBound = rightBound + + +@export +class SubType(VHDLModel_SubType): + def __init__(self, subtypeName: str): + super().__init__(subtypeName) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index af6e5420f..cd2a3e53e 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -33,9 +33,18 @@ from typing import List from pydecor import export -from pyVHDLModel.VHDLModel import Constraint, Direction, Expression, SubTypeOrSymbol + +from pyGHDL.dom.Type import IntegerType, SubType +from pyVHDLModel.VHDLModel import ( + Constraint, + Direction, + Expression, + SubTypeOrSymbol, + BaseType, +) from pyGHDL.libghdl import utils +from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.utils import flist_iter from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode @@ -91,7 +100,7 @@ __all__ = [] @export -def GetSubtypeIndicationFromNode(node, entity: str, name: str) -> SubTypeOrSymbol: +def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubTypeOrSymbol: subTypeIndication = nodes.Get_Subtype_Indication(node) if subTypeIndication is nodes.Null_Iir: return None @@ -124,7 +133,9 @@ def GetSubtypeIndicationFromNode(node, entity: str, name: str) -> SubTypeOrSymbo @export -def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constraint]: +def GetArrayConstraintsFromSubtypeIndication( + subTypeIndication: Iir, +) -> List[Constraint]: constraints = [] for constraint in flist_iter(nodes.Get_Index_Constraint_List(subTypeIndication)): constraintKind = GetIirKindOfNode(constraint) @@ -147,7 +158,23 @@ def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constrai @export -def GetRangeFromNode(node) -> Range: +def GetTypeFromNode(node: Iir) -> BaseType: + typeName = GetNameOfNode(node) + leftBound = IntegerLiteral(0) + rightBound = IntegerLiteral(15) + + return IntegerType(typeName, leftBound, rightBound) + + +@export +def GetSubTypeFromNode(node: Iir) -> BaseType: + subTypeName = GetNameOfNode(node) + + return SubType(subTypeName) + + +@export +def GetRangeFromNode(node: Iir) -> Range: direction = nodes.Get_Direction(node) leftBound = nodes.Get_Left_Limit_Expr(node) rightBound = nodes.Get_Right_Limit_Expr(node) @@ -201,7 +228,7 @@ __EXPRESSION_TRANSLATION = { @export -def GetExpressionFromNode(node) -> Expression: +def GetExpressionFromNode(node: Iir) -> Expression: kind = GetIirKindOfNode(node) try: @@ -218,7 +245,7 @@ def GetExpressionFromNode(node) -> Expression: # FIXME: rewrite to generator @export -def GetGenericsFromChainedNodes(nodeChain): +def GetGenericsFromChainedNodes(nodeChain: Iir): result = [] for generic in utils.chain_iter(nodeChain): kind = GetIirKindOfNode(generic) @@ -240,7 +267,7 @@ def GetGenericsFromChainedNodes(nodeChain): # FIXME: rewrite to generator @export -def GetPortsFromChainedNodes(nodeChain): +def GetPortsFromChainedNodes(nodeChain: Iir): result = [] for port in utils.chain_iter(nodeChain): kind = GetIirKindOfNode(port) @@ -260,7 +287,7 @@ def GetPortsFromChainedNodes(nodeChain): return result -def GetDeclaredItemsFromChainedNodes(nodeChain, entity: str, name: str): +def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str): result = [] for item in utils.chain_iter(nodeChain): kind = GetIirKindOfNode(item) @@ -273,11 +300,9 @@ def GetDeclaredItemsFromChainedNodes(nodeChain, entity: str, name: str): result.append(Signal.parse(item)) elif kind == nodes.Iir_Kind.Anonymous_Type_Declaration: - typeName = GetNameOfNode(item) - print("found type '{name}'".format(name=typeName)) + result.append(GetTypeFromNode(item)) elif kind == nodes.Iir_Kind.Subtype_Declaration: - subTypeName = GetNameOfNode(item) - print("found subtype '{name}'".format(name=subTypeName)) + result.append(GetSubTypeFromNode(item)) elif kind == nodes.Iir_Kind.Function_Declaration: functionName = GetNameOfNode(item) print("found function '{name}'".format(name=functionName)) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 1577edca0..8f95a412e 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -2,6 +2,7 @@ from typing import List, Union from pydecor import export +from pyGHDL.dom.Type import IntegerType, SubType from pyVHDLModel.VHDLModel import ( GenericInterfaceItem, NamedEntity, @@ -293,6 +294,23 @@ class PrettyPrint: else "", ) ) + elif isinstance(item, IntegerType): + buffer.append( + "{prefix}- type {name} is range {range}".format( + prefix=prefix, + name=item.Name, + range="{left!s} to {right!s}".format( + left=item.LeftBound, right=item.RightBound + ), + ) + ) + elif isinstance(item, SubType): + buffer.append( + "{prefix}- subtype {name} is ?????".format( + prefix=prefix, + name=item.Name, + ) + ) else: raise PrettyPrintException("Unhandled declared item kind.") -- cgit v1.2.3 From ed99fae7f13db8d5c3e95e935e32db825313b56a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 15:48:35 +0200 Subject: Prepared handling of functions, types, subtypes and aliases. --- pyGHDL/dom/Misc.py | 124 +------------------------ pyGHDL/dom/NonStandard.py | 171 +++++++++++++++++++++++++++++++++++ pyGHDL/dom/Subprogram.py | 44 +++++++++ pyGHDL/dom/Type.py | 32 +++++++ pyGHDL/dom/_Translate.py | 25 +++-- pyGHDL/dom/formatting/prettyprint.py | 19 +++- 6 files changed, 288 insertions(+), 127 deletions(-) create mode 100644 pyGHDL/dom/NonStandard.py create mode 100644 pyGHDL/dom/Subprogram.py (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Misc.py b/pyGHDL/dom/Misc.py index 7bee2ec7b..8ff62a119 100644 --- a/pyGHDL/dom/Misc.py +++ b/pyGHDL/dom/Misc.py @@ -35,133 +35,19 @@ .. todo:: Add a module documentation. """ -from pathlib import Path -from typing import Any - from pydecor import export -from pyVHDLModel.VHDLModel import Design as VHDLModel_Design -from pyVHDLModel.VHDLModel import Library as VHDLModel_Library -from pyVHDLModel.VHDLModel import Document as VHDLModel_Document - -import pyGHDL.libghdl as libghdl -from pyGHDL.libghdl import ( - name_table, - files_map, - errorout_memory, - LibGHDLException, - utils, +from pyVHDLModel.VHDLModel import ( + Alias as VHDLModel_Alias, ) -from pyGHDL.libghdl.vhdl import nodes, sem_lib, parse from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom.Common import DOMException, GHDLMixin -from pyGHDL.dom.DesignUnit import ( - Entity, - Architecture, - Package, - PackageBody, - Context, - Configuration, -) __all__ = [] @export -class Design(VHDLModel_Design): - def __init__(self): - super().__init__() - - self.__ghdl_init() - - def __ghdl_init(self): - """Initialization: set options and then load libraries""" - # Initialize libghdl - libghdl.finalize() - libghdl.initialize() - - # Collect error messages in memory - errorout_memory.Install_Handler() - - libghdl.set_option("--std=08") - - parse.Flag_Parse_Parenthesis.value = True - - # Finish initialization. This will load the standard package. - if libghdl.analyze_init_status() != 0: - raise LibGHDLException("Error initializing 'libghdl'.") - - -@export -class Library(VHDLModel_Library): - pass - - -@export -class Document(VHDLModel_Document, GHDLMixin): - __ghdlFileID: Any - __ghdlSourceFileEntry: Any - __ghdlFile: Any - - def __init__(self, path: Path = None, dontParse: bool = False): - super().__init__(path) - GHDLMixin.__init__(self) - - self.__ghdl_init() - if dontParse == False: - self.parse() - - def __ghdl_init(self): - # Read input file - self.__ghdlFileID = name_table.Get_Identifier(str(self.Path)) - self.__ghdlSourceFileEntry = files_map.Read_Source_File( - name_table.Null_Identifier, self.__ghdlFileID - ) - if self.__ghdlSourceFileEntry == files_map.No_Source_File_Entry: - raise LibGHDLException("Cannot load file '{!s}'".format(self.Path)) - - self.CheckForErrors() - - # Parse input file - self.__ghdlFile = sem_lib.Load_File(self.__ghdlSourceFileEntry) - - self.CheckForErrors() - - def parse(self): - firstUnit = nodes.Get_First_Design_Unit(self.__ghdlFile) - - for unit in utils.chain_iter(firstUnit): - libraryUnit = nodes.Get_Library_Unit(unit) - nodeKind = GetIirKindOfNode(libraryUnit) - - if nodeKind == nodes.Iir_Kind.Entity_Declaration: - entity = Entity.parse(libraryUnit) - self.Entities.append(entity) - - elif nodeKind == nodes.Iir_Kind.Architecture_Body: - architecture = Architecture.parse(libraryUnit) - self.Architectures.append(architecture) - - elif nodeKind == nodes.Iir_Kind.Package_Declaration: - package = Package.parse(libraryUnit) - self.Packages.append(package) - - elif nodeKind == nodes.Iir_Kind.Package_Body: - packageBody = PackageBody.parse(libraryUnit) - self.PackageBodies.append(packageBody) - - elif nodeKind == nodes.Iir_Kind.Context_Declaration: - context = Context.parse(libraryUnit) - self.Contexts.append(context) - - elif nodeKind == nodes.Iir_Kind.Configuration_Declaration: - configuration = Configuration.parse(libraryUnit) - self.Configurations.append(configuration) - - else: - raise DOMException( - "Unknown design unit kind '{kindName}'({kind}).".format( - kindName=nodeKind.name, kind=nodeKind - ) - ) +class Alias(VHDLModel_Alias): + def __init__(self, aliasName: str): + super().__init__(aliasName) diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py new file mode 100644 index 000000000..c3fd358b5 --- /dev/null +++ b/pyGHDL/dom/NonStandard.py @@ -0,0 +1,171 @@ +# ============================================================================= +# ____ _ _ ____ _ _ +# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___ +# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \ +# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | | +# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_| +# |_| |___/ +# ============================================================================= +# Authors: +# Patrick Lehmann +# +# Package module: DOM: Elements not covered by the VHDL standard. +# +# License: +# ============================================================================ +# Copyright (C) 2019-2021 Tristan Gingold +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# SPDX-License-Identifier: GPL-2.0-or-later +# ============================================================================ + +""" +.. todo:: + Add a module documentation. +""" +from pathlib import Path +from typing import Any + +from pydecor import export + +from pyVHDLModel.VHDLModel import ( + Design as VHDLModel_Design, + Library as VHDLModel_Library, + Document as VHDLModel_Document, +) + +from pyGHDL.libghdl import ( + initialize as libghdl_initialize, + finalize as libghdl_finalize, + set_option as libghdl_set_option, + analyze_init_status as libghdl_analyze_init_status, + name_table, + files_map, + errorout_memory, + LibGHDLException, + utils, +) +from pyGHDL.libghdl.vhdl import nodes, sem_lib, parse +from pyGHDL.dom._Utils import GetIirKindOfNode +from pyGHDL.dom.Common import DOMException, GHDLMixin +from pyGHDL.dom.DesignUnit import ( + Entity, + Architecture, + Package, + PackageBody, + Context, + Configuration, +) + +__all__ = [] + + +@export +class Design(VHDLModel_Design): + def __init__(self): + super().__init__() + + self.__ghdl_init() + + def __ghdl_init(self): + """Initialization: set options and then load libraries""" + # Initialize libghdl + libghdl_finalize() + libghdl_initialize() + + # Collect error messages in memory + errorout_memory.Install_Handler() + + libghdl_set_option("--std=08") + + parse.Flag_Parse_Parenthesis.value = True + + # Finish initialization. This will load the standard package. + if libghdl_analyze_init_status() != 0: + raise LibGHDLException("Error initializing 'libghdl'.") + + +@export +class Library(VHDLModel_Library): + pass + + +@export +class Document(VHDLModel_Document, GHDLMixin): + __ghdlFileID: Any + __ghdlSourceFileEntry: Any + __ghdlFile: Any + + def __init__(self, path: Path = None, dontParse: bool = False): + super().__init__(path) + GHDLMixin.__init__(self) + + self.__ghdl_init() + if dontParse == False: + self.parse() + + def __ghdl_init(self): + # Read input file + self.__ghdlFileID = name_table.Get_Identifier(str(self.Path)) + self.__ghdlSourceFileEntry = files_map.Read_Source_File( + name_table.Null_Identifier, self.__ghdlFileID + ) + if self.__ghdlSourceFileEntry == files_map.No_Source_File_Entry: + raise LibGHDLException("Cannot load file '{!s}'".format(self.Path)) + + self.CheckForErrors() + + # Parse input file + self.__ghdlFile = sem_lib.Load_File(self.__ghdlSourceFileEntry) + + self.CheckForErrors() + + def parse(self): + firstUnit = nodes.Get_First_Design_Unit(self.__ghdlFile) + + for unit in utils.chain_iter(firstUnit): + libraryUnit = nodes.Get_Library_Unit(unit) + nodeKind = GetIirKindOfNode(libraryUnit) + + if nodeKind == nodes.Iir_Kind.Entity_Declaration: + entity = Entity.parse(libraryUnit) + self.Entities.append(entity) + + elif nodeKind == nodes.Iir_Kind.Architecture_Body: + architecture = Architecture.parse(libraryUnit) + self.Architectures.append(architecture) + + elif nodeKind == nodes.Iir_Kind.Package_Declaration: + package = Package.parse(libraryUnit) + self.Packages.append(package) + + elif nodeKind == nodes.Iir_Kind.Package_Body: + packageBody = PackageBody.parse(libraryUnit) + self.PackageBodies.append(packageBody) + + elif nodeKind == nodes.Iir_Kind.Context_Declaration: + context = Context.parse(libraryUnit) + self.Contexts.append(context) + + elif nodeKind == nodes.Iir_Kind.Configuration_Declaration: + configuration = Configuration.parse(libraryUnit) + self.Configurations.append(configuration) + + else: + raise DOMException( + "Unknown design unit kind '{kindName}'({kind}).".format( + kindName=nodeKind.name, kind=nodeKind + ) + ) diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py new file mode 100644 index 000000000..70645df6f --- /dev/null +++ b/pyGHDL/dom/Subprogram.py @@ -0,0 +1,44 @@ +# ============================================================================= +# ____ _ _ ____ _ _ +# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___ +# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \ +# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | | +# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_| +# |_| |___/ +# ============================================================================= +# Authors: +# Patrick Lehmann +# +# Package module: DOM: Interface items (e.g. generic or port) +# +# License: +# ============================================================================ +# Copyright (C) 2019-2021 Tristan Gingold +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# SPDX-License-Identifier: GPL-2.0-or-later +# ============================================================================ +from pydecor import export + +from pyVHDLModel.VHDLModel import ( + Function as VHDLModel_Function, + Expression, +) + + +@export +class Function(VHDLModel_Function): + def __init__(self, functionName: str): + super().__init__(functionName) diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index df143b4d0..c276387c7 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -1,3 +1,35 @@ +# ============================================================================= +# ____ _ _ ____ _ _ +# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___ +# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \ +# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | | +# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_| +# |_| |___/ +# ============================================================================= +# Authors: +# Patrick Lehmann +# +# Package module: DOM: Interface items (e.g. generic or port) +# +# License: +# ============================================================================ +# Copyright (C) 2019-2021 Tristan Gingold +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# SPDX-License-Identifier: GPL-2.0-or-later +# ============================================================================ from pydecor import export from pyVHDLModel.VHDLModel import ( diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index cd2a3e53e..e1770672d 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -34,7 +34,7 @@ from typing import List from pydecor import export -from pyGHDL.dom.Type import IntegerType, SubType +from pyGHDL.dom.Misc import Alias from pyVHDLModel.VHDLModel import ( Constraint, Direction, @@ -49,13 +49,14 @@ from pyGHDL.libghdl.utils import flist_iter from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode from pyGHDL.dom.Common import DOMException -from pyGHDL.dom.Range import Range, RangeExpression from pyGHDL.dom.Symbol import ( SimpleObjectOrFunctionCallSymbol, SimpleSubTypeSymbol, ConstrainedSubTypeSymbol, IndexedObjectOrFunctionCallSymbol, ) +from pyGHDL.dom.Type import IntegerType, SubType +from pyGHDL.dom.Range import Range, RangeExpression from pyGHDL.dom.Literal import ( IntegerLiteral, CharacterLiteral, @@ -95,6 +96,8 @@ from pyGHDL.dom.Expression import ( RotateLeftExpression, RotateRightExpression, ) +from pyGHDL.dom.Subprogram import Function + __all__ = [] @@ -304,14 +307,12 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str): elif kind == nodes.Iir_Kind.Subtype_Declaration: result.append(GetSubTypeFromNode(item)) elif kind == nodes.Iir_Kind.Function_Declaration: - functionName = GetNameOfNode(item) - print("found function '{name}'".format(name=functionName)) + result.append(GetFunctionFromNode(item)) elif kind == nodes.Iir_Kind.Function_Body: # functionName = NodeToName(item) print("found function body '{name}'".format(name="????")) elif kind == nodes.Iir_Kind.Object_Alias_Declaration: - aliasName = GetNameOfNode(item) - print("found alias '{name}'".format(name=aliasName)) + result.append(GetAliasFromNode(item)) else: raise DOMException( "Unknown declared item kind '{kindName}'({kind}) in {entity} '{name}'.".format( @@ -320,3 +321,15 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str): ) return result + + +def GetFunctionFromNode(node: Iir): + functionName = GetNameOfNode(node) + + return Function(functionName) + + +def GetAliasFromNode(node: Iir): + aliasName = GetNameOfNode(node) + + return Alias(aliasName) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 8f95a412e..afbcbb851 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -2,16 +2,17 @@ from typing import List, Union from pydecor import export +from pyGHDL.dom.Misc import Alias from pyGHDL.dom.Type import IntegerType, SubType from pyVHDLModel.VHDLModel import ( GenericInterfaceItem, NamedEntity, PortInterfaceItem, - WithDefaultExpression, + WithDefaultExpression, Function, ) from pyGHDL import GHDLBaseException -from pyGHDL.dom.Misc import Document, Design, Library +from pyGHDL.dom.NonStandard import Document, Design, Library from pyGHDL.dom.DesignUnit import ( Entity, Architecture, @@ -311,6 +312,20 @@ class PrettyPrint: name=item.Name, ) ) + elif isinstance(item, Alias): + buffer.append( + "{prefix}- alias {name} is ?????".format( + prefix=prefix, + name=item.Name, + ) + ) + elif isinstance(item, Function): + buffer.append( + "{prefix}- function {name}".format( + prefix=prefix, + name=item.Name, + ) + ) else: raise PrettyPrintException("Unhandled declared item kind.") -- cgit v1.2.3 From ba097bd3118db3135e75b913cae81973995777cd Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 19:19:11 +0200 Subject: Handle component declarations. --- pyGHDL/dom/DesignUnit.py | 62 ++++++++++++++++++++++++------------ pyGHDL/dom/Literal.py | 1 + pyGHDL/dom/_Translate.py | 6 +++- pyGHDL/dom/formatting/prettyprint.py | 23 +++++++++++-- 4 files changed, 68 insertions(+), 24 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 8e10aa815..53cc03395 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -39,24 +39,25 @@ This module contains all DOM classes for VHDL's design units (:class:`context StringBuffer: + buffer = [] + prefix = " " * level + buffer.append("{prefix}- Component: {name}".format(name=component.Name, prefix=prefix)) + buffer.append("{prefix} Generics:".format(prefix=prefix)) + for generic in component.GenericItems: + for line in self.formatGeneric(generic, level + 1): + buffer.append(line) + buffer.append("{prefix} Ports:".format(prefix=prefix)) + for port in component.PortItems: + for line in self.formatPort(port, level + 1): + buffer.append(line) + + return buffer + def formatPackage(self, package: Package, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level @@ -326,6 +342,9 @@ class PrettyPrint: name=item.Name, ) ) + elif isinstance(item, Component): + for line in self.formatComponent(item, level): + buffer.append(line) else: raise PrettyPrintException("Unhandled declared item kind.") -- cgit v1.2.3 From f0517014231ee735c180a3150b55b878f6af763d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 19:19:50 +0200 Subject: Handle Physical...Literals --- pyGHDL/dom/DesignUnit.py | 21 +++++++++++---------- pyGHDL/dom/Literal.py | 24 ++++++++++++++++++++++++ pyGHDL/dom/_Translate.py | 6 ++++++ pyGHDL/dom/formatting/prettyprint.py | 7 +++++-- 4 files changed, 46 insertions(+), 12 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 53cc03395..ce93bda3e 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -42,13 +42,16 @@ This module contains all DOM classes for VHDL's design units (:class:`context StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}- Component: {name}".format(name=component.Name, prefix=prefix)) + buffer.append( + "{prefix}- Component: {name}".format(name=component.Name, prefix=prefix) + ) buffer.append("{prefix} Generics:".format(prefix=prefix)) for generic in component.GenericItems: for line in self.formatGeneric(generic, level + 1): -- cgit v1.2.3 From ad34fac3f4e30f0ff13e1630b42373f31b2918a4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 21:44:31 +0200 Subject: Fixed function call parameters. Fixed physical literal units. Added basic Procedure detection. --- pyGHDL/dom/Literal.py | 6 +++--- pyGHDL/dom/Subprogram.py | 7 +++++++ pyGHDL/dom/Symbol.py | 3 ++- pyGHDL/dom/_Translate.py | 13 ++++++++++++- pyGHDL/dom/formatting/prettyprint.py | 14 +++++++++++++- 5 files changed, 37 insertions(+), 6 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 4fe3a843c..44c002955 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -30,7 +30,7 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ -from pyGHDL.dom._Utils import GetIirKindOfNode +from pyGHDL.dom._Utils import GetIirKindOfNode, GetNameOfNode from pyGHDL.libghdl import name_table from pyGHDL.libghdl.vhdl import nodes @@ -70,7 +70,7 @@ class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral): def parse(cls, node): value = nodes.Get_Value(node) unit = nodes.Get_Unit_Name(node) - unitName = name_table.Get_Name_Ptr(unit) + unitName = GetNameOfNode(unit) return cls(value, unitName) @@ -81,7 +81,7 @@ class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral): def parse(cls, node): value = nodes.Get_Fp_Value(node) unit = nodes.Get_Unit_Name(node) - unitName = name_table.Get_Name_Ptr(unit) + unitName = GetNameOfNode(unit) return cls(value, unitName) diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py index 70645df6f..4fa6b3e6a 100644 --- a/pyGHDL/dom/Subprogram.py +++ b/pyGHDL/dom/Subprogram.py @@ -34,6 +34,7 @@ from pydecor import export from pyVHDLModel.VHDLModel import ( Function as VHDLModel_Function, + Procedure as VHDLModel_Procedure, Expression, ) @@ -42,3 +43,9 @@ from pyVHDLModel.VHDLModel import ( class Function(VHDLModel_Function): def __init__(self, functionName: str): super().__init__(functionName) + + +@export +class Procedure(VHDLModel_Procedure): + def __init__(self, procedureName: str): + super().__init__(procedureName) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 047fd624f..1865e4481 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -108,7 +108,8 @@ class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSym kind = GetIirKindOfNode(item) if kind == nodes.Iir_Kind.Association_Element_By_Expression: - expr = None # GetExpressionFromNode(nodes.Get_Associated_Expr(item)) + actual = nodes.Get_Actual(item) + expr = GetExpressionFromNode(actual) associations.append(expr) else: diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 7d736f335..ebd650698 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -97,7 +97,7 @@ from pyGHDL.dom.Expression import ( RotateLeftExpression, RotateRightExpression, ) -from pyGHDL.dom.Subprogram import Function +from pyGHDL.dom.Subprogram import Function, Procedure from pyGHDL.dom.Misc import Alias @@ -317,6 +317,11 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str): elif kind == nodes.Iir_Kind.Function_Body: # functionName = NodeToName(item) print("found function body '{name}'".format(name="????")) + elif kind == nodes.Iir_Kind.Procedure_Declaration: + result.append(GetProcedureFromNode(item)) + elif kind == nodes.Iir_Kind.Procedure_Body: + # procedureName = NodeToName(item) + print("found procedure body '{name}'".format(name="????")) elif kind == nodes.Iir_Kind.Object_Alias_Declaration: result.append(GetAliasFromNode(item)) elif kind == nodes.Iir_Kind.Component_Declaration: @@ -339,6 +344,12 @@ def GetFunctionFromNode(node: Iir): return Function(functionName) +def GetProcedureFromNode(node: Iir): + procedureName = GetNameOfNode(node) + + return Procedure(procedureName) + + def GetAliasFromNode(node: Iir): aliasName = GetNameOfNode(node) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index cdb1964c0..13f18f729 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -3,6 +3,7 @@ from typing import List, Union from pydecor import export from pyGHDL.dom.Misc import Alias +from pyGHDL.dom.Subprogram import Procedure from pyGHDL.dom.Type import IntegerType, SubType from pyVHDLModel.VHDLModel import ( GenericInterfaceItem, @@ -345,11 +346,22 @@ class PrettyPrint: name=item.Name, ) ) + elif isinstance(item, Procedure): + buffer.append( + "{prefix}- procedure {name}".format( + prefix=prefix, + name=item.Name, + ) + ) elif isinstance(item, Component): for line in self.formatComponent(item, level): buffer.append(line) else: - raise PrettyPrintException("Unhandled declared item kind.") + raise PrettyPrintException( + "Unhandled declared item kind '{name}'.".format( + name=item.__class__.__name__ + ) + ) return buffer -- cgit v1.2.3 From 11bd75f611a892af0e20e913a9580d43c23e610b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 22:36:07 +0200 Subject: Print position where exception happened. --- pyGHDL/dom/Misc.py | 26 +++++++++++++-- pyGHDL/dom/Subprogram.py | 14 ++++++++ pyGHDL/dom/_Translate.py | 83 +++++++++++++++++++++++++++++++----------------- pyGHDL/dom/_Utils.py | 22 ++++++++++--- 4 files changed, 110 insertions(+), 35 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Misc.py b/pyGHDL/dom/Misc.py index 8ff62a119..8bea6cf61 100644 --- a/pyGHDL/dom/Misc.py +++ b/pyGHDL/dom/Misc.py @@ -41,12 +41,34 @@ from pyVHDLModel.VHDLModel import ( Alias as VHDLModel_Alias, ) -from pyGHDL.dom._Utils import GetIirKindOfNode -from pyGHDL.dom.Common import DOMException, GHDLMixin __all__ = [] +@export +class Position: + _filename: str + _line: int + _column: int + + def __init__(self, filename: str, line: int, column: int): + self._filename = filename + self._line = line + self._column = column + + @property + def Filename(self): + return self._filename + + @property + def Line(self): + return self._line + + @property + def Column(self): + return self._column + + @export class Alias(VHDLModel_Alias): def __init__(self, aliasName: str): diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py index 4fa6b3e6a..420041a52 100644 --- a/pyGHDL/dom/Subprogram.py +++ b/pyGHDL/dom/Subprogram.py @@ -32,11 +32,13 @@ # ============================================================================ from pydecor import export +from pyGHDL.dom._Utils import GetNameOfNode from pyVHDLModel.VHDLModel import ( Function as VHDLModel_Function, Procedure as VHDLModel_Procedure, Expression, ) +from pyGHDL.libghdl._types import Iir @export @@ -44,8 +46,20 @@ class Function(VHDLModel_Function): def __init__(self, functionName: str): super().__init__(functionName) + @classmethod + def parse(cls, node: Iir): + functionName = GetNameOfNode(node) + + return cls(functionName) + @export class Procedure(VHDLModel_Procedure): def __init__(self, procedureName: str): super().__init__(procedureName) + + @classmethod + def parse(cls, node: Iir): + procedureName = GetNameOfNode(node) + + return cls(procedureName) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index ebd650698..84d3448d7 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -44,9 +44,8 @@ from pyVHDLModel.VHDLModel import ( from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir -from pyGHDL.libghdl.utils import flist_iter from pyGHDL.libghdl.vhdl import nodes -from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode +from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode, GetPositionOfNode from pyGHDL.dom.Common import DOMException from pyGHDL.dom.Symbol import ( SimpleObjectOrFunctionCallSymbol, @@ -128,9 +127,16 @@ def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubTypeOr ) ) else: + position = GetPositionOfNode(node) raise DOMException( - "Unknown subtype kind '{kind}' of subtype indication '{indication}' while parsing {entity} '{name}'.".format( - kind=subTypeKind, indication=subTypeIndication, entity=entity, name=name + "Unknown subtype kind '{kind}' of subtype indication '{indication}' while parsing {entity} '{name}' at {file}:{line}:{column}.".format( + kind=subTypeKind, + indication=subTypeIndication, + entity=entity, + name=name, + file=position.Filename, + line=position.Line, + column=position.Column, ) ) @@ -142,7 +148,9 @@ def GetArrayConstraintsFromSubtypeIndication( subTypeIndication: Iir, ) -> List[Constraint]: constraints = [] - for constraint in flist_iter(nodes.Get_Index_Constraint_List(subTypeIndication)): + for constraint in utils.flist_iter( + nodes.Get_Index_Constraint_List(subTypeIndication) + ): constraintKind = GetIirKindOfNode(constraint) if constraintKind == nodes.Iir_Kind.Range_Expression: constraints.append(RangeExpression(GetRangeFromNode(constraint))) @@ -151,11 +159,15 @@ def GetArrayConstraintsFromSubtypeIndication( elif constraintKind == nodes.Iir_Kind.Simple_Name: raise DOMException("[NOT IMPLEMENTED] Subtype as range.") else: + position = GetPositionOfNode(constraint) raise DOMException( - "Unknown constraint kind '{kind}' for constraint '{constraint}' in subtype indication '{indication}'.".format( + "Unknown constraint kind '{kind}' for constraint '{constraint}' in subtype indication '{indication}' at {file}:{line}:{column}.".format( kind=constraintKind, constraint=constraint, indication=subTypeIndication, + file=position.Filename, + line=position.Line, + column=position.Column, ) ) @@ -241,9 +253,15 @@ def GetExpressionFromNode(node: Iir) -> Expression: try: cls = __EXPRESSION_TRANSLATION[kind] except KeyError: + position = GetPositionOfNode(node) raise DOMException( - "Unknown expression kind '{kindName}'({kind}) in expression '{expr}'.".format( - kind=kind, kindName=kind.name, expr=node + "Unknown expression kind '{kindName}'({kind}) in expression '{expr}' at {file}:{line}:{column}.".format( + kind=kind, + kindName=kind.name, + expr=node, + file=position.Filename, + line=position.Line, + column=position.Column, ) ) @@ -263,9 +281,15 @@ def GetGenericsFromChainedNodes(nodeChain: Iir): result.append(genericConstant) else: + position = GetPositionOfNode(generic) raise DOMException( - "Unknown generic kind '{kindName}'({kind}) in generic '{generic}'.".format( - kind=kind, kindName=kind.name, generic=generic + "Unknown generic kind '{kindName}'({kind}) in generic '{generic}' at {file}:{line}:{column}.".format( + kind=kind, + kindName=kind.name, + generic=generic, + file=position.Filename, + line=position.Line, + column=position.Column, ) ) @@ -285,9 +309,15 @@ def GetPortsFromChainedNodes(nodeChain: Iir): result.append(portSignal) else: + position = GetPositionOfNode(port) raise DOMException( - "Unknown port kind '{kindName}'({kind}) in port '{port}'.".format( - kind=kind, kindName=kind.name, port=port + "Unknown port kind '{kindName}'({kind}) in port '{port}' at {file}:{line}:{column}.".format( + kind=kind, + kindName=kind.name, + port=port, + file=position.Filename, + line=position.Line, + column=position.Column, ) ) @@ -313,12 +343,12 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str): elif kind == nodes.Iir_Kind.Subtype_Declaration: result.append(GetSubTypeFromNode(item)) elif kind == nodes.Iir_Kind.Function_Declaration: - result.append(GetFunctionFromNode(item)) + result.append(Function.parse(item)) elif kind == nodes.Iir_Kind.Function_Body: - # functionName = NodeToName(item) + # procedureName = NodeToName(item) print("found function body '{name}'".format(name="????")) elif kind == nodes.Iir_Kind.Procedure_Declaration: - result.append(GetProcedureFromNode(item)) + result.append(Procedure.parse(item)) elif kind == nodes.Iir_Kind.Procedure_Body: # procedureName = NodeToName(item) print("found procedure body '{name}'".format(name="????")) @@ -329,27 +359,22 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str): result.append(Component.parse(item)) else: + position = GetPositionOfNode(item) raise DOMException( - "Unknown declared item kind '{kindName}'({kind}) in {entity} '{name}'.".format( - kind=kind, kindName=kind.name, entity=entity, name=name + "Unknown declared item kind '{kindName}'({kind}) in {entity} '{name}' at {file}:{line}:{column}.".format( + kind=kind, + kindName=kind.name, + entity=entity, + name=name, + file=position.Filename, + line=position.Line, + column=position.Column, ) ) return result -def GetFunctionFromNode(node: Iir): - functionName = GetNameOfNode(node) - - return Function(functionName) - - -def GetProcedureFromNode(node: Iir): - procedureName = GetNameOfNode(node) - - return Procedure(procedureName) - - def GetAliasFromNode(node: Iir): aliasName = GetNameOfNode(node) diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index b5cf1fc5c..e0d97f892 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -30,12 +30,14 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from pyGHDL.libghdl._types import Iir from pydecor import export from pyVHDLModel.VHDLModel import Mode -from pyGHDL.libghdl import LibGHDLException, name_table +from pyGHDL.libghdl import LibGHDLException, name_table, files_map from pyGHDL.libghdl.vhdl import nodes +from pyGHDL.dom.Misc import Position __all__ = [] @@ -50,22 +52,34 @@ __MODE_TRANSLATION = { @export -def GetIirKindOfNode(node) -> nodes.Iir_Kind: +def GetIirKindOfNode(node: Iir) -> nodes.Iir_Kind: kind: int = nodes.Get_Kind(node) return nodes.Iir_Kind(kind) @export -def GetNameOfNode(node) -> str: +def GetNameOfNode(node: Iir) -> str: """Return the python string from node :obj:`node` identifier""" identifier = nodes.Get_Identifier(node) return name_table.Get_Name_Ptr(identifier) @export -def GetModeOfNode(node) -> Mode: +def GetModeOfNode(node: Iir) -> Mode: """Return the mode of a :obj:`port`.""" try: return __MODE_TRANSLATION[nodes.Get_Mode(node)] except KeyError: raise LibGHDLException("Unknown mode.") + + +@export +def GetPositionOfNode(node: Iir) -> Position: + location = nodes.Get_Location(node) + file = files_map.Location_To_File(location) + fileName = name_table.Get_Name_Ptr(file) + # position = files_map.Location_File_To_Pos(location, file) + line = files_map.Location_File_To_Line(location, file) + column = files_map.Location_File_Line_To_Offset(location, file, line) + + return Position(fileName, line, column) -- cgit v1.2.3 From f956044c3045992f37f23d88d9e51a1de8593948 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 23:18:29 +0200 Subject: Implemented handling of generic parameters to subprograms. --- pyGHDL/dom/InterfaceItem.py | 109 +++++++++++++++++++++++++++++++---- pyGHDL/dom/Subprogram.py | 42 ++++++++++++-- pyGHDL/dom/_Translate.py | 32 ++++++++++ pyGHDL/dom/formatting/prettyprint.py | 5 +- 4 files changed, 171 insertions(+), 17 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index 6c0d2641b..eac92c8a6 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -30,28 +30,30 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ -from pyGHDL.libghdl.vhdl.nodes import Null_Iir - -from pyGHDL.libghdl.vhdl import nodes from pydecor import export from pyVHDLModel.VHDLModel import ( GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem, PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem, + ParameterConstantInterfaceItem as VHDLModel_ParameterConstantInterfaceItem, + ParameterVariableInterfaceItem as VHDLModel_ParameterVariableInterfaceItem, + ParameterSignalInterfaceItem as VHDLModel_ParameterSignalInterfaceItem, Mode, SubTypeOrSymbol, Expression, ) +from pyGHDL.libghdl.vhdl import nodes +from pyGHDL.libghdl.vhdl.nodes import Null_Iir from pyGHDL.dom._Utils import GetNameOfNode, GetModeOfNode from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode -from pyGHDL.dom.Common import GHDLMixin + __all__ = [] @export -class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLMixin): +class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem): @classmethod def parse(cls, generic): name = GetNameOfNode(generic) @@ -60,9 +62,9 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLM default = nodes.Get_Default_Value(generic) value = GetExpressionFromNode(default) if default else None - generic = cls(name, mode, subTypeIndication, value) + g = cls(name, mode, subTypeIndication, value) - return generic + return g def __init__( self, @@ -77,7 +79,7 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLM @export -class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin): +class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem): @classmethod def parse(cls, port): name = GetNameOfNode(port) @@ -89,9 +91,96 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin): GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None ) - port = cls(name, mode, subTypeIndication, value) + p = cls(name, mode, subTypeIndication, value) + + return p + + def __init__( + self, + name: str, + mode: Mode, + subType: SubTypeOrSymbol, + defaultExpression: Expression = None, + ): + super().__init__(name=name, mode=mode) + self._subType = subType + self._defaultExpression = defaultExpression + + +@export +class ParameterConstantInterfaceItem(VHDLModel_ParameterConstantInterfaceItem): + @classmethod + def parse(cls, parameter): + name = GetNameOfNode(parameter) + mode = GetModeOfNode(parameter) + subTypeIndication = GetSubtypeIndicationFromNode(parameter, "parameter", name) + + defaultValue = nodes.Get_Default_Value(parameter) + value = ( + GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None + ) + + param = cls(name, mode, subTypeIndication, value) + + return param + + def __init__( + self, + name: str, + mode: Mode, + subType: SubTypeOrSymbol, + defaultExpression: Expression = None, + ): + super().__init__(name=name, mode=mode) + self._subType = subType + self._defaultExpression = defaultExpression + + +@export +class ParameterVariableInterfaceItem(VHDLModel_ParameterVariableInterfaceItem): + @classmethod + def parse(cls, parameter): + name = GetNameOfNode(parameter) + mode = GetModeOfNode(parameter) + subTypeIndication = GetSubtypeIndicationFromNode(parameter, "parameter", name) + + defaultValue = nodes.Get_Default_Value(parameter) + value = ( + GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None + ) + + param = cls(name, mode, subTypeIndication, value) + + return param + + def __init__( + self, + name: str, + mode: Mode, + subType: SubTypeOrSymbol, + defaultExpression: Expression = None, + ): + super().__init__(name=name, mode=mode) + self._subType = subType + self._defaultExpression = defaultExpression + + +@export +class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem): + @classmethod + def parse(cls, parameter): + name = GetNameOfNode(parameter) + mode = GetModeOfNode(parameter) + subTypeIndication = GetSubtypeIndicationFromNode(parameter, "parameter", name) + + defaultValue = nodes.Get_Default_Value(parameter) + value = ( + GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None + ) + + param = cls(name, mode, subTypeIndication, value) - return port + return param def __init__( self, diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py index 420041a52..b3c47bfe5 100644 --- a/pyGHDL/dom/Subprogram.py +++ b/pyGHDL/dom/Subprogram.py @@ -30,27 +30,47 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from pyGHDL.dom.Symbol import SimpleSubTypeSymbol +from pyGHDL.libghdl.vhdl import nodes from pydecor import export from pyGHDL.dom._Utils import GetNameOfNode from pyVHDLModel.VHDLModel import ( Function as VHDLModel_Function, Procedure as VHDLModel_Procedure, - Expression, + SubTypeOrSymbol, ) from pyGHDL.libghdl._types import Iir @export class Function(VHDLModel_Function): - def __init__(self, functionName: str): + def __init__(self, functionName: str, returnType: SubTypeOrSymbol): super().__init__(functionName) + self._returnType = returnType @classmethod def parse(cls, node: Iir): + from pyGHDL.dom._Translate import ( + GetGenericsFromChainedNodes, + GetParameterFromChainedNodes, + ) + functionName = GetNameOfNode(node) + returnType = nodes.Get_Return_Type_Mark(node) + returnTypeName = GetNameOfNode(returnType) + + returnTypeSymbol = SimpleSubTypeSymbol(returnTypeName) + function = cls(functionName, returnTypeSymbol) + + for generic in GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(node)): + function.GenericItems.append(generic) + for port in GetParameterFromChainedNodes( + nodes.Get_Interface_Declaration_Chain(node) + ): + function.ParameterItems.append(port) - return cls(functionName) + return function @export @@ -60,6 +80,20 @@ class Procedure(VHDLModel_Procedure): @classmethod def parse(cls, node: Iir): + from pyGHDL.dom._Translate import ( + GetGenericsFromChainedNodes, + GetParameterFromChainedNodes, + ) + procedureName = GetNameOfNode(node) - return cls(procedureName) + procedure = cls(procedureName) + + for generic in GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(node)): + procedure.GenericItems.append(generic) + for port in GetParameterFromChainedNodes( + nodes.Get_Interface_Declaration_Chain(node) + ): + procedure.ParameterItems.append(port) + + return procedure diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 84d3448d7..4e5baa9cf 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -324,6 +324,38 @@ def GetPortsFromChainedNodes(nodeChain: Iir): return result +# FIXME: rewrite to generator +@export +def GetParameterFromChainedNodes(nodeChain: Iir): + result = [] + for parameter in utils.chain_iter(nodeChain): + kind = GetIirKindOfNode(parameter) + if kind == nodes.Iir_Kind.Interface_Constant_Declaration: + pass + elif kind == nodes.Iir_Kind.Interface_Variable_Declaration: + pass + elif kind == nodes.Iir_Kind.Interface_Signal_Declaration: + from pyGHDL.dom.InterfaceItem import PortSignalInterfaceItem + + portSignal = ParameterSignalInterfaceItem.parse(parameter) + + result.append(portSignal) + else: + position = GetPositionOfNode(parameter) + raise DOMException( + "Unknown parameter kind '{kindName}'({kind}) in parameter '{param}' at {file}:{line}:{column}.".format( + kind=kind, + kindName=kind.name, + param=parameter, + file=position.Filename, + line=position.Line, + column=position.Column, + ) + ) + + return result + + def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str): result = [] for item in utils.chain_iter(nodeChain): diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 13f18f729..f19125811 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -341,9 +341,8 @@ class PrettyPrint: ) elif isinstance(item, Function): buffer.append( - "{prefix}- function {name}".format( - prefix=prefix, - name=item.Name, + "{prefix}- function {name} return {returnType!s}".format( + prefix=prefix, name=item.Name, returnType=item.ReturnType ) ) elif isinstance(item, Procedure): -- cgit v1.2.3 From ef92aeca1b940e26b8fb6d562dcc74b06bb450f8 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 22 Jun 2021 09:08:14 +0200 Subject: Fixed filename in error messages. --- pyGHDL/dom/_Utils.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index e0d97f892..38a85c0c3 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -77,7 +77,7 @@ def GetModeOfNode(node: Iir) -> Mode: def GetPositionOfNode(node: Iir) -> Position: location = nodes.Get_Location(node) file = files_map.Location_To_File(location) - fileName = name_table.Get_Name_Ptr(file) + fileName = name_table.Get_Name_Ptr(files_map.Get_File_Name(file)) # position = files_map.Location_File_To_Pos(location, file) line = files_map.Location_File_To_Line(location, file) column = files_map.Location_File_Line_To_Offset(location, file, line) -- cgit v1.2.3 From 0a69901be945dfb6c5372e657332d5e5ddfa10c7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 22 Jun 2021 11:59:09 +0200 Subject: Fixed issues reported by Codacy. --- pyGHDL/dom/Expression.py | 7 ------- pyGHDL/dom/Literal.py | 7 +++---- pyGHDL/dom/NonStandard.py | 3 ++- pyGHDL/dom/_Translate.py | 14 ++++++++------ 4 files changed, 13 insertions(+), 18 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 2802351d4..b129e1ce5 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -167,13 +167,6 @@ class FunctionCall(VHDLModel_FunctionCall): self._operand = operand -@export -class QualifiedExpression(VHDLModel_QualifiedExpression): - def __init__(self, operand: Expression): - super().__init__() - self._operand = operand - - @export class AdditionExpression(VHDLModel_AdditionExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 44c002955..209712ba3 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -30,10 +30,6 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ -from pyGHDL.dom._Utils import GetIirKindOfNode, GetNameOfNode -from pyGHDL.libghdl import name_table - -from pyGHDL.libghdl.vhdl import nodes from pydecor import export from pyVHDLModel.VHDLModel import ( @@ -44,6 +40,9 @@ from pyVHDLModel.VHDLModel import ( CharacterLiteral as VHDLModel_CharacterLiteral, StringLiteral as VHDLModel_StringLiteral, ) +from pyGHDL.libghdl import name_table +from pyGHDL.libghdl.vhdl import nodes +from pyGHDL.dom._Utils import GetNameOfNode __all__ = [] diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index c3fd358b5..9010e392b 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -80,7 +80,8 @@ class Design(VHDLModel_Design): self.__ghdl_init() def __ghdl_init(self): - """Initialization: set options and then load libraries""" + """Initialization: set options and then load libraries.""" + # Initialize libghdl libghdl_finalize() libghdl_initialize() diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 4e5baa9cf..2b2a44e60 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -331,15 +331,17 @@ def GetParameterFromChainedNodes(nodeChain: Iir): for parameter in utils.chain_iter(nodeChain): kind = GetIirKindOfNode(parameter) if kind == nodes.Iir_Kind.Interface_Constant_Declaration: - pass + from pyGHDL.dom.InterfaceItem import ParameterConstantInterfaceItem + + result.append(ParameterConstantInterfaceItem.parse(parameter)) elif kind == nodes.Iir_Kind.Interface_Variable_Declaration: - pass - elif kind == nodes.Iir_Kind.Interface_Signal_Declaration: - from pyGHDL.dom.InterfaceItem import PortSignalInterfaceItem + from pyGHDL.dom.InterfaceItem import ParameterVariableInterfaceItem - portSignal = ParameterSignalInterfaceItem.parse(parameter) + result.append(ParameterVariableInterfaceItem.parse(parameter)) + elif kind == nodes.Iir_Kind.Interface_Signal_Declaration: + from pyGHDL.dom.InterfaceItem import ParameterSignalInterfaceItem - result.append(portSignal) + result.append(ParameterSignalInterfaceItem.parse(parameter)) else: position = GetPositionOfNode(parameter) raise DOMException( -- cgit v1.2.3