From 2b25719bf3a5880f428b5a58b17208b8e71eba8a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 26 Jun 2021 13:54:59 +0200 Subject: Added missing import. --- pyGHDL/dom/DesignUnit.py | 1 + pyGHDL/dom/__init__.py | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index a8249d38d..c4f19deef 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -59,6 +59,7 @@ from pyVHDLModel.VHDLModel import ( PortInterfaceItem, EntityOrSymbol, Name, + ConcurrentStatement, ) from pyGHDL.libghdl.vhdl import nodes diff --git a/pyGHDL/dom/__init__.py b/pyGHDL/dom/__init__.py index 19f23a94b..d3dc506f5 100644 --- a/pyGHDL/dom/__init__.py +++ b/pyGHDL/dom/__init__.py @@ -46,7 +46,6 @@ __all__ = [] @export class Position: """Represents the source code position of a IIR node in a source file.""" - _filename: Path _line: int _column: int -- cgit v1.2.3 From 2492b5595c7a61e29096a217e46f9dfe2e0fd6ac Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 26 Jun 2021 10:02:16 +0200 Subject: WIP: Handle more generic interface kinds. (cherry picked from commit 6b5606852371bdd8bdc9c8a3dcd38ef8e7eecbc9) --- pyGHDL/dom/InterfaceItem.py | 92 ++++++++++++++++++++++++++++++++++++++++----- pyGHDL/dom/_Translate.py | 15 ++++++-- pyGHDL/dom/__init__.py | 8 ++-- 3 files changed, 97 insertions(+), 18 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index df62c8256..c5955c6aa 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -34,6 +34,10 @@ from pydecor import export from pyVHDLModel.VHDLModel import ( GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem, + GenericTypeInterfaceItem as VHDLModel_GenericTypeInterfaceItem, + GenericPackageInterfaceItem as VHDLModel_GenericPackageInterfaceItem, + GenericProcedureInterfaceItem as VHDLModel_GenericProcedureInterfaceItem, + GenericFunctionInterfaceItem as VHDLModel_GenericFunctionInterfaceItem, PortSignalInterfaceItem as VHDLModel_PortSignalInterfaceItem, ParameterConstantInterfaceItem as VHDLModel_ParameterConstantInterfaceItem, ParameterVariableInterfaceItem as VHDLModel_ParameterVariableInterfaceItem, @@ -64,13 +68,9 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMi subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name=name, mode=mode) + super().__init__(name, mode, subType, defaultExpression) DOMMixin.__init__(self, node) - # TODO: move to model - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, genericNode: Iir) -> "GenericConstantInterfaceItem": name = GetNameOfNode(genericNode) @@ -82,6 +82,82 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMi return cls(genericNode, name, mode, subTypeIndication, value) +@export +class GenericTypeInterfaceItem(VHDLModel_GenericTypeInterfaceItem, DOMMixin): + def __init__( + self, + node: Iir, + name: str, + ): + super().__init__(name=name) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, genericNode: Iir) -> "GenericTypeInterfaceItem": + name = GetNameOfNode(genericNode) + + return cls(genericNode, name) + + +@export +class GenericPackageInterfaceItem(VHDLModel_GenericPackageInterfaceItem, DOMMixin): + def __init__( + self, + node: Iir, + name: str, + ): + super().__init__(name) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, genericNode: Iir) -> "GenericPackageInterfaceItem": + name = GetNameOfNode(genericNode) + + return cls(genericNode, name) + + +@export +class GenericProcedureInterfaceItem(VHDLModel_GenericProcedureInterfaceItem, DOMMixin): + def __init__( + self, + node: Iir, + name: str, + ): + super().__init__(name) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, genericNode: Iir) -> "GenericProcedureInterfaceItem": + name = GetNameOfNode(genericNode) + mode = GetModeOfNode(genericNode) + subTypeIndication = GetSubTypeIndicationFromNode(genericNode, "generic", name) + default = nodes.Get_Default_Value(genericNode) + value = GetExpressionFromNode(default) if default else None + + return cls(genericNode, name) + + +@export +class GenericFunctionInterfaceItem(VHDLModel_GenericFunctionInterfaceItem, DOMMixin): + def __init__( + self, + node: Iir, + name: str, + ): + super().__init__(name) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, genericNode: Iir) -> "GenericFunctionInterfaceItem": + name = GetNameOfNode(genericNode) + mode = GetModeOfNode(genericNode) + subTypeIndication = GetSubTypeIndicationFromNode(genericNode, "generic", name) + default = nodes.Get_Default_Value(genericNode) + value = GetExpressionFromNode(default) if default else None + + return cls(genericNode, name) + + @export class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin): def __init__( @@ -92,13 +168,9 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin): subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name=name, mode=mode) + super().__init__(name, mode, subType, defaultExpression) DOMMixin.__init__(self, node) - # TODO: move to model - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, portNode: Iir) -> "PortSignalInterfaceItem": name = GetNameOfNode(portNode) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 502a94ad3..806b6f2fa 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -416,6 +416,13 @@ def GetExpressionFromNode(node: Iir) -> Expression: def GetGenericsFromChainedNodes( nodeChain: Iir, ) -> Generator[GenericInterfaceItem, None, None]: + from pyGHDL.dom.InterfaceItem import ( + GenericTypeInterfaceItem, + GenericPackageInterfaceItem, + GenericProcedureInterfaceItem, + GenericFunctionInterfaceItem, + ) + for generic in utils.chain_iter(nodeChain): kind = GetIirKindOfNode(generic) if kind == nodes.Iir_Kind.Interface_Constant_Declaration: @@ -423,13 +430,13 @@ def GetGenericsFromChainedNodes( yield GenericConstantInterfaceItem.parse(generic) elif kind == nodes.Iir_Kind.Interface_Type_Declaration: - print("[NOT IMPLEMENTED] generic type") + yield GenericTypeInterfaceItem.parse(generic) elif kind == nodes.Iir_Kind.Interface_Package_Declaration: - print("[NOT IMPLEMENTED] generic package") + yield GenericPackageInterfaceItem.parse(generic) elif kind == nodes.Iir_Kind.Interface_Procedure_Declaration: - print("[NOT IMPLEMENTED] generic procedure") + yield GenericProcedureInterfaceItem.parse(generic) elif kind == nodes.Iir_Kind.Interface_Function_Declaration: - print("[NOT IMPLEMENTED] generic function") + yield GenericFunctionInterfaceItem.parse(generic) else: position = Position.parse(generic) raise DOMException( diff --git a/pyGHDL/dom/__init__.py b/pyGHDL/dom/__init__.py index d3dc506f5..143fab1ff 100644 --- a/pyGHDL/dom/__init__.py +++ b/pyGHDL/dom/__init__.py @@ -32,13 +32,12 @@ # ============================================================================ from pathlib import Path -from pyGHDL import GHDLBaseException -from pyGHDL.libghdl import files_map, name_table - -from pyGHDL.libghdl.vhdl import nodes from pydecor import export +from pyGHDL import GHDLBaseException +from pyGHDL.libghdl import files_map, name_table from pyGHDL.libghdl._types import Iir +from pyGHDL.libghdl.vhdl import nodes __all__ = [] @@ -46,6 +45,7 @@ __all__ = [] @export class Position: """Represents the source code position of a IIR node in a source file.""" + _filename: Path _line: int _column: int -- cgit v1.2.3 From 06e53f991bee84c881cbea64bb9f7067d9d033fc Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 26 Jun 2021 18:47:45 +0200 Subject: Fix Codacy problems. --- pyGHDL/dom/Expression.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index b3256d551..e34feb31c 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -530,7 +530,7 @@ class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) - subType = SimpleSubTypeSymbol(typeMarkName) + subType = SimpleSubTypeSymbol(node, typeMarkName) operand = GetExpressionFromNode(nodes.Get_Expression(node)) return cls(subType, operand) -- cgit v1.2.3 From 2b8408086015c15c105c3a173e9485c19e391980 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 27 Jun 2021 11:03:32 +0200 Subject: Current state. --- pyGHDL/dom/Symbol.py | 25 +++++++++++++------------ pyGHDL/dom/formatting/prettyprint.py | 4 ++-- 2 files changed, 15 insertions(+), 14 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 85d1c637b..af6c1beb6 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -47,7 +47,6 @@ from pyVHDLModel.VHDLModel import ( ) from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin -from pyGHDL.dom._Utils import GetNameOfNode from pyGHDL.dom.Range import Range @@ -56,15 +55,15 @@ __all__ = [] @export class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin): - def __init__(self, node: Iir, entityName: str): + def __init__(self, node: Iir, entityName: Name): super().__init__(entityName) DOMMixin.__init__(self, node) @export class EnumerationLiteralSymbol(VHDLModel_EnumerationLiteralSymbol, DOMMixin): - def __init__(self, node: Iir, literalName: str): - super().__init__(symbolName=literalName) + def __init__(self, node: Iir, literalName: Name): + super().__init__(literalName) DOMMixin.__init__(self, node) @@ -82,8 +81,8 @@ class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol, DOMMixin): class ConstrainedScalarSubTypeSymbol( VHDLModel_ConstrainedScalarSubTypeSymbol, DOMMixin ): - def __init__(self, node: Iir, subTypeName: str, range: Range = None): - super().__init__(subTypeName=subTypeName, range=range) + def __init__(self, node: Iir, subTypeName: Name, rng: Range = None): + super().__init__(subTypeName, rng) DOMMixin.__init__(self, node) @classmethod @@ -96,9 +95,9 @@ class ConstrainedCompositeSubTypeSymbol( VHDLModel_ConstrainedCompositeSubTypeSymbol, DOMMixin ): def __init__( - self, node: Iir, subTypeName: str, constraints: List[Constraint] = None + self, node: Iir, subTypeName: Name, constraints: List[Constraint] = None ): - super().__init__(subTypeName=subTypeName, constraints=constraints) + super().__init__(subTypeName, constraints) DOMMixin.__init__(self, node) @classmethod @@ -112,7 +111,9 @@ class SimpleObjectOrFunctionCallSymbol( ): @classmethod def parse(cls, node: Iir): - name = GetNameOfNode(node) + from pyGHDL.dom._Translate import GetNameFromNode + + name = GetNameFromNode(node) return cls(name) @@ -120,13 +121,13 @@ class SimpleObjectOrFunctionCallSymbol( class IndexedObjectOrFunctionCallSymbol( VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin ): - def __init__(self, node: Iir, name: str): - super().__init__(objectName=name) + def __init__(self, node: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, node) @classmethod def parse(cls, node: Iir): - from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameFromNode + from pyGHDL.dom._Translate import GetNameFromNode name = GetNameFromNode(node) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index f055f3f51..fb1fcf826 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -21,7 +21,7 @@ from pyVHDLModel.VHDLModel import ( GenericInterfaceItem, NamedEntity, PortInterfaceItem, - WithDefaultExpression, + WithDefaultExpressionMixin, Function, BaseType, Type, @@ -481,7 +481,7 @@ class PrettyPrint: ) ) - def formatInitialValue(self, item: WithDefaultExpression) -> str: + def formatInitialValue(self, item: WithDefaultExpressionMixin) -> str: if item.DefaultExpression is None: return "" -- cgit v1.2.3 From 5c2afa1e06c43e4f445e3387b3de77231b6c42d4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 27 Jun 2021 22:46:28 +0200 Subject: Fixed MRO problems. --- pyGHDL/dom/InterfaceItem.py | 6 +----- pyGHDL/dom/Object.py | 33 ++++++--------------------------- pyGHDL/dom/formatting/prettyprint.py | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+), 32 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index c5955c6aa..97ef0cfe8 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -199,13 +199,9 @@ class ParameterConstantInterfaceItem( subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name, mode) + super().__init__(name, mode, subType, defaultExpression) DOMMixin.__init__(self, node) - # TODO: move to model - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, parameterNode: Iir) -> "ParameterConstantInterfaceItem": name = GetNameOfNode(parameterNode) diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py index 3085f9f81..0358f716d 100644 --- a/pyGHDL/dom/Object.py +++ b/pyGHDL/dom/Object.py @@ -62,13 +62,9 @@ class Constant(VHDLModel_Constant, DOMMixin): subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name) + super().__init__(name, subType, defaultExpression) DOMMixin.__init__(self, node) - self._name = name - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, constantNode: Iir) -> Union["Constant", "DeferredConstant"]: from pyGHDL.dom._Translate import ( @@ -90,12 +86,9 @@ class Constant(VHDLModel_Constant, DOMMixin): @export class DeferredConstant(VHDLModel_DeferredConstant, DOMMixin): def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name) + super().__init__(name, subType) DOMMixin.__init__(self, node) - self._name = name - self._subType = subType - @classmethod def parse(cls, constantNode: Iir) -> "DeferredConstant": from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode @@ -117,13 +110,9 @@ class Variable(VHDLModel_Variable, DOMMixin): subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name) + super().__init__(name, subType, defaultExpression) DOMMixin.__init__(self, node) - self._name = name - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, variableNode: Iir) -> "Variable": from pyGHDL.dom._Translate import ( @@ -144,12 +133,9 @@ class Variable(VHDLModel_Variable, DOMMixin): @export class SharedVariable(VHDLModel_SharedVariable, DOMMixin): def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name) + super().__init__(name, subType) DOMMixin.__init__(self, node) - self._name = name - self._subType = subType - @classmethod def parse(cls, variableNode: Iir) -> "SharedVariable": from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode @@ -169,13 +155,9 @@ class Signal(VHDLModel_Signal, DOMMixin): subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name) + super().__init__(name, subType, defaultExpression) DOMMixin.__init__(self, node) - self._name = name - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, signalNode: Iir) -> "Signal": from pyGHDL.dom._Translate import ( @@ -194,12 +176,9 @@ class Signal(VHDLModel_Signal, DOMMixin): @export class File(VHDLModel_File, DOMMixin): def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name) + super().__init__(name, subType) DOMMixin.__init__(self, node) - self._name = name - self._subType = subType - @classmethod def parse(cls, fileNode: Iir) -> "File": from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index fb1fcf826..cddfec458 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -44,6 +44,7 @@ from pyGHDL.dom.Object import Constant, Signal, SharedVariable, File from pyGHDL.dom.InterfaceItem import ( GenericConstantInterfaceItem, PortSignalInterfaceItem, + GenericTypeInterfaceItem, ) from pyGHDL.dom.Symbol import ( SimpleSubTypeSymbol, @@ -262,6 +263,8 @@ class PrettyPrint: ) -> StringBuffer: if isinstance(generic, GenericConstantInterfaceItem): return self.formatGenericConstant(generic, level) + elif isinstance(generic, GenericTypeInterfaceItem): + return self.formatGenericType(generic, level) else: raise PrettyPrintException( "Unhandled generic kind for generic '{name}'.".format(name=generic.Name) @@ -297,6 +300,21 @@ class PrettyPrint: return buffer + def formatGenericType( + self, generic: GenericConstantInterfaceItem, level: int = 0 + ) -> StringBuffer: + buffer = [] + prefix = " " * level + + buffer.append( + "{prefix} - type {name}".format( + prefix=prefix, + name=generic.Name, + ) + ) + + return buffer + def formatPortSignal( self, port: PortSignalInterfaceItem, level: int = 0 ) -> StringBuffer: -- cgit v1.2.3 From da38f9732a89d9394f18a04eb721a6383e12646c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 28 Jun 2021 09:42:11 +0200 Subject: Minor improvements. --- pyGHDL/dom/Expression.py | 245 ++++++++++++++--------------------------------- 1 file changed, 71 insertions(+), 174 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index e34feb31c..2dd82ed97 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -96,7 +96,7 @@ from pyGHDL.dom.Aggregates import ( __all__ = [] -class _ParseUnaryExpression: +class _ParseUnaryExpressionMixin: @classmethod def parse(cls, node: Iir): from pyGHDL.dom._Translate import GetExpressionFromNode @@ -105,7 +105,7 @@ class _ParseUnaryExpression: return cls(node, operand) -class _ParseBinaryExpression: +class _ParseBinaryExpressionMixin: @classmethod def parse(cls, node: Iir): from pyGHDL.dom._Translate import GetExpressionFromNode @@ -116,51 +116,41 @@ class _ParseBinaryExpression: @export -class InverseExpression(VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpression): +class InverseExpression(VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: Expression): - super().__init__() + super().__init__(operand) DOMMixin.__init__(self, node) - self._operand = operand - @export -class IdentityExpression(VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpression): +class IdentityExpression(VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: Expression): - super().__init__() + super().__init__(operand) DOMMixin.__init__(self, node) - self._operand = operand - @export -class NegationExpression(VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpression): +class NegationExpression(VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: Expression): - super().__init__() + super().__init__(operand) DOMMixin.__init__(self, node) - self._operand = operand - @export -class AbsoluteExpression(VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpression): +class AbsoluteExpression(VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: Expression): - super().__init__() + super().__init__(operand) DOMMixin.__init__(self, node) - self._operand = operand - @export class ParenthesisExpression( - VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpression + VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpressionMixin ): def __init__(self, node: Iir, operand: Expression): - super().__init__() + super().__init__(operand) DOMMixin.__init__(self, node) - self._operand = operand - @classmethod def parse(cls, node: Iir): from pyGHDL.dom._Translate import GetExpressionFromNode @@ -172,11 +162,9 @@ class ParenthesisExpression( @export class TypeConversion(VHDLModel_TypeConversion, DOMMixin): def __init__(self, node: Iir, operand: Expression): - super().__init__() + super().__init__(operand) DOMMixin.__init__(self, node) - self._operand = operand - @export class FunctionCall(VHDLModel_FunctionCall, DOMMixin): @@ -184,8 +172,6 @@ class FunctionCall(VHDLModel_FunctionCall, DOMMixin): super().__init__() DOMMixin.__init__(self, node) - self._operand = operand - class RangeExpression(VHDLModel_RangeExpression, DOMMixin): @classmethod @@ -205,326 +191,239 @@ class RangeExpression(VHDLModel_RangeExpression, DOMMixin): @export class AscendingRangeExpression(VHDLModel_AscendingRangeExpression, DOMMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class AdditionExpression( - VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class SubtractionExpression( - VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class ConcatenationExpression( - VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class MultiplyExpression( - VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class DivisionExpression( - VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class RemainderExpression( - VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class ModuloExpression(VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpression): +class ModuloExpression(VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class ExponentiationExpression( - VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpression): +class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpression): +class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpression): +class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpression): +class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpression): +class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpression): +class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpression): +class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export -class UnequalExpression(VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpression): +class UnequalExpression(VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class LessThanExpression( - VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class LessEqualExpression( - VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class GreaterThanExpression( - VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class GreaterEqualExpression( - VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class ShiftRightLogicExpression( - VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class ShiftLeftLogicExpression( - VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class ShiftRightArithmeticExpression( - VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class ShiftLeftArithmeticExpression( - VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class RotateRightExpression( - VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class RotateLeftExpression( - VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpression + VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpressionMixin ): def __init__(self, node: Iir, left: Expression, right: Expression): - super().__init__() + super().__init__(left, right) DOMMixin.__init__(self, node) - self._leftOperand = left - self._rightOperand = right - @export class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): def __init__(self, node: Iir, subType: SubTypeOrSymbol, operand: Expression): - super().__init__() + super().__init__(subType, operand) DOMMixin.__init__(self, node) - self._subtype = subType - self._operand = operand - @classmethod def parse(cls, node: Iir): from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode @@ -532,17 +431,15 @@ class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) subType = SimpleSubTypeSymbol(node, typeMarkName) operand = GetExpressionFromNode(nodes.Get_Expression(node)) - return cls(subType, operand) + return cls(node, subType, operand) @export class Aggregate(VHDLModel_Aggregate, DOMMixin): def __init__(self, node: Iir, elements: List[AggregateElement]): - super().__init__() + super().__init__(elements) DOMMixin.__init__(self, node) - self._elements = elements - @classmethod def parse(cls, node: Iir): from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode @@ -563,7 +460,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): r = GetRangeFromNode(nodes.Get_Choice_Range(item)) choices.append(RangedAggregateElement(item, r, value)) elif kind == nodes.Iir_Kind.Choice_By_Name: - name = EnumerationLiteralSymbol(nodes.Get_Choice_Name(item)) + name = EnumerationLiteralSymbol(item, nodes.Get_Choice_Name(item)) choices.append(NamedAggregateElement(item, name, value)) elif kind == nodes.Iir_Kind.Choice_By_Others: choices.append(OthersAggregateElement(item, value)) -- cgit v1.2.3 From 3c26dd63f093e156c9bf4143aeddafd3a4664ecc Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 28 Jun 2021 12:51:06 +0200 Subject: Reworked symbols. --- pyGHDL/dom/Aggregates.py | 28 +++++++--------------------- pyGHDL/dom/Expression.py | 38 ++++++++++++++++++++++++++++---------- pyGHDL/dom/Symbol.py | 8 -------- 3 files changed, 35 insertions(+), 39 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py index 32dc1cacf..8edd037a1 100644 --- a/pyGHDL/dom/Aggregates.py +++ b/pyGHDL/dom/Aggregates.py @@ -48,12 +48,11 @@ from pyVHDLModel.VHDLModel import ( NamedAggregateElement as VHDLModel_NamedAggregateElement, OthersAggregateElement as VHDLModel_OthersAggregateElement, Expression, + Symbol, ) from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin from pyGHDL.dom.Range import Range -from pyGHDL.dom.Symbol import EnumerationLiteralSymbol - __all__ = [] @@ -61,43 +60,30 @@ __all__ = [] @export class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin): def __init__(self, node: Iir, expression: Expression): - super().__init__() + super().__init__(expression) DOMMixin.__init__(self, node) - self._expression = expression - @export class IndexedAggregateElement(VHDLModel_IndexedAggregateElement, DOMMixin): def __init__(self, node: Iir, index: Expression, expression: Expression): - super().__init__() + super().__init__(index, expression) DOMMixin.__init__(self, node) - self._index = index - self._expression = expression - @export class RangedAggregateElement(VHDLModel_RangedAggregateElement, DOMMixin): - def __init__(self, node: Iir, r: Range, expression: Expression): - super().__init__() + def __init__(self, node: Iir, rng: Range, expression: Expression): + super().__init__(rng, expression) DOMMixin.__init__(self, node) - self._range = r - self._expression = expression - @export class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin): - def __init__( - self, node: Iir, name: EnumerationLiteralSymbol, expression: Expression - ): - super().__init__() + def __init__(self, node: Iir, name: Symbol, expression: Expression): + super().__init__(name, expression) DOMMixin.__init__(self, node) - self._name = name - self._expression = expression - @export class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin): diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 2dd82ed97..3dc1271f2 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -77,13 +77,14 @@ from pyVHDLModel.VHDLModel import ( Expression, AggregateElement, SubTypeOrSymbol, + Symbol, ) from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import GetIirKindOfNode -from pyGHDL.dom.Symbol import EnumerationLiteralSymbol, SimpleSubTypeSymbol +from pyGHDL.dom.Symbol import SimpleSubTypeSymbol from pyGHDL.dom.Aggregates import ( OthersAggregateElement, SimpleAggregateElement, @@ -116,28 +117,36 @@ class _ParseBinaryExpressionMixin: @export -class InverseExpression(VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin): +class InverseExpression( + VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin +): def __init__(self, node: Iir, operand: Expression): super().__init__(operand) DOMMixin.__init__(self, node) @export -class IdentityExpression(VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin): +class IdentityExpression( + VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin +): def __init__(self, node: Iir, operand: Expression): super().__init__(operand) DOMMixin.__init__(self, node) @export -class NegationExpression(VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin): +class NegationExpression( + VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin +): def __init__(self, node: Iir, operand: Expression): super().__init__(operand) DOMMixin.__init__(self, node) @export -class AbsoluteExpression(VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin): +class AbsoluteExpression( + VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin +): def __init__(self, node: Iir, operand: Expression): super().__init__(operand) DOMMixin.__init__(self, node) @@ -257,7 +266,9 @@ class RemainderExpression( @export -class ModuloExpression(VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin): +class ModuloExpression( + VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin +): def __init__(self, node: Iir, left: Expression, right: Expression): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -322,7 +333,9 @@ class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressio @export -class UnequalExpression(VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin): +class UnequalExpression( + VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin +): def __init__(self, node: Iir, left: Expression, right: Expression): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -442,7 +455,11 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): @classmethod def parse(cls, node: Iir): - from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode + from pyGHDL.dom._Translate import ( + GetExpressionFromNode, + GetRangeFromNode, + GetNameFromNode, + ) choices = [] @@ -460,8 +477,9 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): r = GetRangeFromNode(nodes.Get_Choice_Range(item)) choices.append(RangedAggregateElement(item, r, value)) elif kind == nodes.Iir_Kind.Choice_By_Name: - name = EnumerationLiteralSymbol(item, nodes.Get_Choice_Name(item)) - choices.append(NamedAggregateElement(item, name, value)) + name = GetNameFromNode(nodes.Get_Choice_Name(item)) + symbol = Symbol(item, name) + choices.append(NamedAggregateElement(item, symbol, value)) elif kind == nodes.Iir_Kind.Choice_By_Others: choices.append(OthersAggregateElement(item, value)) else: diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index af6c1beb6..be8dd362e 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -39,7 +39,6 @@ from pyVHDLModel.VHDLModel import ( SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, ConstrainedScalarSubTypeSymbol as VHDLModel_ConstrainedScalarSubTypeSymbol, ConstrainedCompositeSubTypeSymbol as VHDLModel_ConstrainedCompositeSubTypeSymbol, - EnumerationLiteralSymbol as VHDLModel_EnumerationLiteralSymbol, SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol, IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol, Constraint, @@ -60,13 +59,6 @@ class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin): DOMMixin.__init__(self, node) -@export -class EnumerationLiteralSymbol(VHDLModel_EnumerationLiteralSymbol, DOMMixin): - def __init__(self, node: Iir, literalName: Name): - super().__init__(literalName) - DOMMixin.__init__(self, node) - - @export class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol, DOMMixin): def __init__(self, node: Iir, subTypeName: Name): -- cgit v1.2.3 From e8556a64e6ad3cedbe4862e6be992f516536abf7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 28 Jun 2021 17:24:40 +0200 Subject: Rework and fine tuning. --- pyGHDL/dom/InterfaceItem.py | 31 +++-------------- pyGHDL/dom/Type.py | 14 ++++++++ pyGHDL/dom/_Translate.py | 67 ++++++++++++++++++++++++++++-------- pyGHDL/dom/__init__.py | 5 +++ pyGHDL/dom/formatting/prettyprint.py | 41 +++++++++++++++++++--- 5 files changed, 112 insertions(+), 46 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index 97ef0cfe8..31e2058cb 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -89,7 +89,7 @@ class GenericTypeInterfaceItem(VHDLModel_GenericTypeInterfaceItem, DOMMixin): node: Iir, name: str, ): - super().__init__(name=name) + super().__init__(name) DOMMixin.__init__(self, node) @classmethod @@ -129,10 +129,6 @@ class GenericProcedureInterfaceItem(VHDLModel_GenericProcedureInterfaceItem, DOM @classmethod def parse(cls, genericNode: Iir) -> "GenericProcedureInterfaceItem": name = GetNameOfNode(genericNode) - mode = GetModeOfNode(genericNode) - subTypeIndication = GetSubTypeIndicationFromNode(genericNode, "generic", name) - default = nodes.Get_Default_Value(genericNode) - value = GetExpressionFromNode(default) if default else None return cls(genericNode, name) @@ -150,10 +146,6 @@ class GenericFunctionInterfaceItem(VHDLModel_GenericFunctionInterfaceItem, DOMMi @classmethod def parse(cls, genericNode: Iir) -> "GenericFunctionInterfaceItem": name = GetNameOfNode(genericNode) - mode = GetModeOfNode(genericNode) - subTypeIndication = GetSubTypeIndicationFromNode(genericNode, "generic", name) - default = nodes.Get_Default_Value(genericNode) - value = GetExpressionFromNode(default) if default else None return cls(genericNode, name) @@ -232,13 +224,9 @@ class ParameterVariableInterfaceItem( subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name, mode) + super().__init__(name, mode, subType, defaultExpression) DOMMixin.__init__(self, node) - # TODO: move to model - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, parameterNode: Iir) -> "ParameterVariableInterfaceItem": name = GetNameOfNode(parameterNode) @@ -267,13 +255,9 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name, mode) + super().__init__(name, mode, subType, defaultExpression) DOMMixin.__init__(self, node) - # TODO: move to model - self._subType = subType - self._defaultExpression = defaultExpression - @classmethod def parse(cls, parameterNode: Iir) -> "ParameterSignalInterfaceItem": name = GetNameOfNode(parameterNode) @@ -298,21 +282,16 @@ class ParameterFileInterfaceItem(VHDLModel_ParameterFileInterfaceItem, DOMMixin) self, node: Iir, name: str, - mode: Mode, subType: SubTypeOrSymbol, ): - super().__init__(name, mode) + super().__init__(name, subType) DOMMixin.__init__(self, node) - # TODO: move to model - self._subType = subType - @classmethod def parse(cls, parameterNode: Iir) -> "ParameterFileInterfaceItem": name = GetNameOfNode(parameterNode) - mode = GetModeOfNode(parameterNode) subTypeIndication = GetSubTypeIndicationFromNode( parameterNode, "parameter", name ) - return cls(parameterNode, name, mode, subTypeIndication) + return cls(parameterNode, name, subTypeIndication) diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index db51f1c49..ba774f079 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -35,6 +35,7 @@ from typing import List, Union, Iterator, Tuple from pydecor import export from pyVHDLModel.VHDLModel import ( + AnonymousType as VHDLModel_AnonymousType, PhysicalType as VHDLModel_PhysicalType, IntegerType as VHDLModel_IntegerType, EnumeratedType as VHDLModel_EnumeratedType, @@ -59,6 +60,19 @@ from pyGHDL.dom.Range import Range from pyGHDL.dom.Subprogram import Function, Procedure +@export +class IncompleteType(VHDLModel_AnonymousType, DOMMixin): + def __init__(self, node: Iir, name: str): + super().__init__(name) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, node: Iir) -> "IncompleteType": + name = GetNameOfNode(node) + + return cls(node, name) + + @export class EnumeratedType(VHDLModel_EnumeratedType, DOMMixin): def __init__(self, node: Iir, name: str, literals: List[EnumerationLiteral]): diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 806b6f2fa..6cc993de7 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -81,6 +81,7 @@ from pyGHDL.dom.Type import ( ProtectedTypeBody, FileType, PhysicalType, + IncompleteType, ) from pyGHDL.dom.Range import Range from pyGHDL.dom.Literal import ( @@ -217,22 +218,14 @@ def GetArrayConstraintsFromSubtypeIndication( def GetTypeFromNode(node: Iir) -> BaseType: typeName = GetNameOfNode(node) typeDefinition = nodes.Get_Type_Definition(node) + if typeDefinition is nodes.Null_Iir: + return IncompleteType(node, typeName) kind = GetIirKindOfNode(typeDefinition) - if kind == nodes.Iir_Kind.Range_Expression: - r = GetRangeFromNode(typeDefinition) - - return IntegerType(node, typeName, r) - elif kind == nodes.Iir_Kind.Physical_Type_Definition: - return PhysicalType.parse(typeName, typeDefinition) - elif kind == nodes.Iir_Kind.Enumeration_Type_Definition: + if kind == nodes.Iir_Kind.Enumeration_Type_Definition: return EnumeratedType.parse(typeName, typeDefinition) elif kind == nodes.Iir_Kind.Array_Type_Definition: return ArrayType.parse(typeName, typeDefinition) - elif kind == nodes.Iir_Kind.Array_Subtype_Definition: - print("[NOT IMPLEMENTED] Array_Subtype_Definition") - - return ArrayType(typeDefinition, "????", [], None) elif kind == nodes.Iir_Kind.Record_Type_Definition: return RecordType.parse(typeName, typeDefinition) elif kind == nodes.Iir_Kind.Access_Type_Definition: @@ -244,9 +237,41 @@ def GetTypeFromNode(node: Iir) -> BaseType: else: position = Position.parse(typeDefinition) raise DOMException( - "Unknown type definition kind '{kindName}'({kind}) for type '{name}' at {file}:{line}:{column}.".format( - kind=kind, - kindName=kind.name, + "GetTypeFromNode: Unknown type definition kind '{kind}' for type '{name}' at {file}:{line}:{column}.".format( + kind=kind.name, + name=typeName, + file=position.Filename, + line=position.Line, + column=position.Column, + ) + ) + + +@export +def GetAnonymousTypeFromNode(node: Iir) -> BaseType: + typeName = GetNameOfNode(node) + typeDefinition = nodes.Get_Type_Definition(node) + if typeDefinition is nodes.Null_Iir: + print(1, node, typeName) + return IncompleteType(node, typeName) + + kind = GetIirKindOfNode(typeDefinition) + if kind == nodes.Iir_Kind.Range_Expression: + r = GetRangeFromNode(typeDefinition) + return IntegerType(node, typeName, r) + + elif kind == nodes.Iir_Kind.Physical_Type_Definition: + return PhysicalType.parse(typeName, typeDefinition) + + elif kind == nodes.Iir_Kind.Array_Subtype_Definition: + print("[NOT IMPLEMENTED] Array_Subtype_Definition") + + return ArrayType(typeDefinition, "????", [], None) + else: + position = Position.parse(typeDefinition) + raise DOMException( + "GetAnonymousTypeFromNode: Unknown type definition kind '{kind}' for type '{name}' at {file}:{line}:{column}.".format( + kind=kind.name, name=typeName, file=position.Filename, line=position.Line, @@ -541,12 +566,16 @@ def GetDeclaredItemsFromChainedNodes( yield File.parse(item) elif kind == nodes.Iir_Kind.Type_Declaration: yield GetTypeFromNode(item) + elif kind == nodes.Iir_Kind.Anonymous_Type_Declaration: - yield GetTypeFromNode(item) + yield GetAnonymousTypeFromNode(item) + elif kind == nodes.Iir_Kind.Subtype_Declaration: yield GetSubTypeFromNode(item) + elif kind == nodes.Iir_Kind.Function_Declaration: yield Function.parse(item) + elif kind == nodes.Iir_Kind.Function_Body: # procedureName = NodeToName(item) print("found function body '{name}'".format(name="????")) @@ -585,6 +614,14 @@ def GetDeclaredItemsFromChainedNodes( name=name ) ) + elif kind == nodes.Iir_Kind.Group_Declaration: + print("[NOT IMPLEMENTED] Group declaration in {name}".format(name=name)) + elif kind == nodes.Iir_Kind.Group_Template_Declaration: + print( + "[NOT IMPLEMENTED] Group template declaration in {name}".format( + name=name + ) + ) else: position = Position.parse(item) raise DOMException( diff --git a/pyGHDL/dom/__init__.py b/pyGHDL/dom/__init__.py index 143fab1ff..20c90a1d1 100644 --- a/pyGHDL/dom/__init__.py +++ b/pyGHDL/dom/__init__.py @@ -84,6 +84,11 @@ class Position: def Column(self) -> int: return self._column + def __str__(self): + return "{file}:{line}:{column}".format( + file=self._filename, line=self._line, column=self._column + ) + @export class DOMMixin: diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index cddfec458..f7994b36d 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -16,6 +16,7 @@ from pyGHDL.dom.Type import ( ProtectedType, ProtectedTypeBody, PhysicalType, + IncompleteType, ) from pyVHDLModel.VHDLModel import ( GenericInterfaceItem, @@ -24,7 +25,7 @@ from pyVHDLModel.VHDLModel import ( WithDefaultExpressionMixin, Function, BaseType, - Type, + FullType, ) from pyGHDL import GHDLBaseException @@ -97,7 +98,12 @@ class PrettyPrint: # buffer.append(line) buffer.append("{prefix}Packages:".format(prefix=prefix)) for package in library.Packages: - for line in self.formatPackage(package, level + 1): + if isinstance(package, Package): + gen = self.formatPackage + else: + gen = self.formatPackageInstance + + for line in gen(package, level + 1): buffer.append(line) # buffer.append("{prefix}PackageBodies:".format(prefix=prefix)) # for packageBodies in library.PackageBodies: @@ -127,7 +133,12 @@ class PrettyPrint: buffer.append(line) buffer.append("{prefix}Packages:".format(prefix=prefix)) for package in document.Packages: - for line in self.formatPackage(package, level + 1): + if isinstance(package, Package): + gen = self.formatPackage + else: + gen = self.formatPackageInstance + + for line in gen(package, level + 1): buffer.append(line) buffer.append("{prefix}PackageBodies:".format(prefix=prefix)) for packageBodies in document.PackageBodies: @@ -225,6 +236,24 @@ class PrettyPrint: return buffer + def formatPackageInstance( + self, package: PackageInstantiation, level: int = 0 + ) -> StringBuffer: + buffer = [] + prefix = " " * level + buffer.append("{prefix}- Name: {name}".format(name=package.Name, prefix=prefix)) + buffer.append( + "{prefix} Package: {name!s}".format( + prefix=prefix, name=package.PackageReference + ) + ) + buffer.append("{prefix} Generic Map: ...".format(prefix=prefix)) + # for item in package.GenericItems: + # for line in self.formatGeneric(item, level + 1): + # buffer.append(line) + + return buffer + def formatPackageBody( self, packageBody: PackageBody, level: int = 0 ) -> StringBuffer: @@ -383,7 +412,7 @@ class PrettyPrint: ), ) ) - elif isinstance(item, Type): + elif isinstance(item, (FullType, IncompleteType)): buffer.append( "{prefix}- {type}".format(prefix=prefix, type=self.formatType(item)) ) @@ -454,7 +483,9 @@ class PrettyPrint: def formatType(self, item: BaseType) -> str: result = "type {name} is ".format(name=item.Name) - if isinstance(item, IntegerType): + if isinstance(item, IncompleteType): + result += "" + elif isinstance(item, IntegerType): result += "range {left!s} to {right!s}".format( left=item.LeftBound, right=item.RightBound ) -- cgit v1.2.3 From 6df51cb7d14d8e29d5aad0883d748f38f53115f1 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 08:41:40 +0200 Subject: Renamed '_?[nN]ame: str' to '_?[iI]dentifier: str'. --- pyGHDL/dom/Attribute.py | 4 +-- pyGHDL/dom/DesignUnit.py | 32 +++++++++---------- pyGHDL/dom/InterfaceItem.py | 36 +++++++++++----------- pyGHDL/dom/Names.py | 20 ++++++------ pyGHDL/dom/Object.py | 24 +++++++-------- pyGHDL/dom/Type.py | 36 +++++++++++----------- pyGHDL/dom/formatting/prettyprint.py | 60 ++++++++++++++++++------------------ 7 files changed, 106 insertions(+), 106 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py index 8c7b08190..3fef7494c 100644 --- a/pyGHDL/dom/Attribute.py +++ b/pyGHDL/dom/Attribute.py @@ -48,8 +48,8 @@ from pyGHDL.dom.Symbol import SimpleSubTypeSymbol @export class Attribute(VHDLModel_Attribute, DOMMixin): - def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name, subType) + def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): + super().__init__(identifier, subType) DOMMixin.__init__(self, node) @classmethod diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index c4f19deef..54816aef1 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -96,13 +96,13 @@ class Entity(VHDLModel_Entity, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, genericItems: List[GenericInterfaceItem] = None, portItems: List[PortInterfaceItem] = None, declaredItems: List = None, bodyItems: List["ConcurrentStatement"] = None, ): - super().__init__(name, genericItems, portItems, declaredItems, bodyItems) + super().__init__(identifier, genericItems, portItems, declaredItems, bodyItems) DOMMixin.__init__(self, node) @classmethod @@ -123,12 +123,12 @@ class Architecture(VHDLModel_Architecture, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, entity: EntityOrSymbol, declaredItems: List = None, bodyItems: List["ConcurrentStatement"] = None, ): - super().__init__(name, entity, declaredItems, bodyItems) + super().__init__(identifier, entity, declaredItems, bodyItems) DOMMixin.__init__(self, node) @classmethod @@ -153,11 +153,11 @@ class Component(VHDLModel_Component, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, genericItems: List[GenericInterfaceItem] = None, portItems: List[PortInterfaceItem] = None, ): - super().__init__(name, genericItems, portItems) + super().__init__(identifier, genericItems, portItems) DOMMixin.__init__(self, node) @classmethod @@ -174,11 +174,11 @@ class Package(VHDLModel_Package, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, genericItems: List[GenericInterfaceItem] = None, declaredItems: List = None, ): - super().__init__(name, genericItems, declaredItems) + super().__init__(identifier, genericItems, declaredItems) DOMMixin.__init__(self, node) @classmethod @@ -205,10 +205,10 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, declaredItems: List = None, ): - super().__init__(name, declaredItems) + super().__init__(identifier, declaredItems) DOMMixin.__init__(self, node) @classmethod @@ -226,11 +226,11 @@ class PackageInstantiation(VHDLModel_PackageInstantiation, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, uninstantiatedPackageName: Name, # genericItems: List[GenericInterfaceItem] = None, ): - super().__init__(name, uninstantiatedPackageName) + super().__init__(identifier, uninstantiatedPackageName) DOMMixin.__init__(self, node) @classmethod @@ -249,9 +249,9 @@ class Context(VHDLModel_Context, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, ): - super().__init__(name) + super().__init__(identifier) DOMMixin.__init__(self, node) @classmethod @@ -268,9 +268,9 @@ class Configuration(VHDLModel_Configuration, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, ): - super().__init__(name) + super().__init__(identifier) DOMMixin.__init__(self, node) @classmethod diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index 31e2058cb..72f79d694 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -63,12 +63,12 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMi def __init__( self, node: Iir, - name: str, + identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name, mode, subType, defaultExpression) + super().__init__(identifier, mode, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -87,9 +87,9 @@ class GenericTypeInterfaceItem(VHDLModel_GenericTypeInterfaceItem, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, ): - super().__init__(name) + super().__init__(identifier) DOMMixin.__init__(self, node) @classmethod @@ -121,9 +121,9 @@ class GenericProcedureInterfaceItem(VHDLModel_GenericProcedureInterfaceItem, DOM def __init__( self, node: Iir, - name: str, + identifier: str, ): - super().__init__(name) + super().__init__(identifier) DOMMixin.__init__(self, node) @classmethod @@ -138,9 +138,9 @@ class GenericFunctionInterfaceItem(VHDLModel_GenericFunctionInterfaceItem, DOMMi def __init__( self, node: Iir, - name: str, + identifier: str, ): - super().__init__(name) + super().__init__(identifier) DOMMixin.__init__(self, node) @classmethod @@ -155,12 +155,12 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name, mode, subType, defaultExpression) + super().__init__(identifier, mode, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -186,12 +186,12 @@ class ParameterConstantInterfaceItem( def __init__( self, node: Iir, - name: str, + identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name, mode, subType, defaultExpression) + super().__init__(identifier, mode, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -219,12 +219,12 @@ class ParameterVariableInterfaceItem( def __init__( self, node: Iir, - name: str, + identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name, mode, subType, defaultExpression) + super().__init__(identifier, mode, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -250,12 +250,12 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi def __init__( self, node: Iir, - name: str, + identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(name, mode, subType, defaultExpression) + super().__init__(identifier, mode, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -281,10 +281,10 @@ class ParameterFileInterfaceItem(VHDLModel_ParameterFileInterfaceItem, DOMMixin) def __init__( self, node: Iir, - name: str, + identifier: str, subType: SubTypeOrSymbol, ): - super().__init__(name, subType) + super().__init__(identifier, subType) DOMMixin.__init__(self, node) @classmethod diff --git a/pyGHDL/dom/Names.py b/pyGHDL/dom/Names.py index fa53acae6..e09294d40 100644 --- a/pyGHDL/dom/Names.py +++ b/pyGHDL/dom/Names.py @@ -52,8 +52,8 @@ __all__ = [] @export class SimpleName(VHDLModel_SimpleName, DOMMixin): - def __init__(self, node: Iir, name: str): - super().__init__(name) + def __init__(self, node: Iir, identifier: str): + super().__init__(identifier) DOMMixin.__init__(self, node) @@ -66,29 +66,29 @@ class ParenthesisName(VHDLModel_ParenthesisName, DOMMixin): @export class IndexedName(VHDLModel_IndexedName, DOMMixin): - def __init__(self, node: Iir, name: str): - super().__init__(name) + def __init__(self, node: Iir, identifier: str): + super().__init__(identifier) DOMMixin.__init__(self, node) @export class SlicedName(VHDLModel_SlicedName, DOMMixin): - def __init__(self, node: Iir, name: str): - super().__init__(name) + def __init__(self, node: Iir, identifier: str): + super().__init__(identifier) DOMMixin.__init__(self, node) @export class SelectedName(VHDLModel_SelectedName, DOMMixin): - def __init__(self, node: Iir, name: str, prefix: Name): - super().__init__(name, prefix) + def __init__(self, node: Iir, identifier: str, prefix: Name): + super().__init__(identifier, prefix) DOMMixin.__init__(self, node) @export class AttributeName(VHDLModel_AttributeName, DOMMixin): - def __init__(self, node: Iir, name: str, prefix: Name): - super().__init__(name, prefix) + def __init__(self, node: Iir, identifier: str, prefix: Name): + super().__init__(identifier, prefix) DOMMixin.__init__(self, node) diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py index 0358f716d..97bfdaa82 100644 --- a/pyGHDL/dom/Object.py +++ b/pyGHDL/dom/Object.py @@ -58,11 +58,11 @@ class Constant(VHDLModel_Constant, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name, subType, defaultExpression) + super().__init__(identifier, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -85,8 +85,8 @@ class Constant(VHDLModel_Constant, DOMMixin): @export class DeferredConstant(VHDLModel_DeferredConstant, DOMMixin): - def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name, subType) + def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): + super().__init__(identifier, subType) DOMMixin.__init__(self, node) @classmethod @@ -106,11 +106,11 @@ class Variable(VHDLModel_Variable, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name, subType, defaultExpression) + super().__init__(identifier, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -132,8 +132,8 @@ class Variable(VHDLModel_Variable, DOMMixin): @export class SharedVariable(VHDLModel_SharedVariable, DOMMixin): - def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name, subType) + def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): + super().__init__(identifier, subType) DOMMixin.__init__(self, node) @classmethod @@ -151,11 +151,11 @@ class Signal(VHDLModel_Signal, DOMMixin): def __init__( self, node: Iir, - name: str, + identifier: str, subType: SubTypeOrSymbol, defaultExpression: Expression, ): - super().__init__(name, subType, defaultExpression) + super().__init__(identifier, subType, defaultExpression) DOMMixin.__init__(self, node) @classmethod @@ -175,8 +175,8 @@ class Signal(VHDLModel_Signal, DOMMixin): @export class File(VHDLModel_File, DOMMixin): - def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name, subType) + def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): + super().__init__(identifier, subType) DOMMixin.__init__(self, node) @classmethod diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index ba774f079..ea4765ed1 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -62,8 +62,8 @@ from pyGHDL.dom.Subprogram import Function, Procedure @export class IncompleteType(VHDLModel_AnonymousType, DOMMixin): - def __init__(self, node: Iir, name: str): - super().__init__(name) + def __init__(self, node: Iir, identifier: str): + super().__init__(identifier) DOMMixin.__init__(self, node) @classmethod @@ -75,8 +75,8 @@ class IncompleteType(VHDLModel_AnonymousType, DOMMixin): @export class EnumeratedType(VHDLModel_EnumeratedType, DOMMixin): - def __init__(self, node: Iir, name: str, literals: List[EnumerationLiteral]): - super().__init__(name, literals) + def __init__(self, node: Iir, identifier: str, literals: List[EnumerationLiteral]): + super().__init__(identifier, literals) DOMMixin.__init__(self, node) @classmethod @@ -135,9 +135,9 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): @export class ArrayType(VHDLModel_ArrayType, DOMMixin): def __init__( - self, node: Iir, name: str, indices: List, elementSubType: SubTypeOrSymbol + self, node: Iir, identifier: str, indices: List, elementSubType: SubTypeOrSymbol ): - super().__init__(name, indices, elementSubType) + super().__init__(identifier, indices, elementSubType) DOMMixin.__init__(self, node) @classmethod @@ -173,8 +173,8 @@ class ArrayType(VHDLModel_ArrayType, DOMMixin): @export class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin): - def __init__(self, node: Iir, name: str, subType: SubTypeOrSymbol): - super().__init__(name, subType) + def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): + super().__init__(identifier, subType) DOMMixin.__init__(self, node) @classmethod @@ -191,8 +191,8 @@ class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin): @export class RecordType(VHDLModel_RecordType, DOMMixin): - def __init__(self, node: Iir, name: str, elements: List[RecordTypeElement] = None): - super().__init__(name, elements) + def __init__(self, node: Iir, identifier: str, elements: List[RecordTypeElement] = None): + super().__init__(identifier, elements) DOMMixin.__init__(self, node) @classmethod @@ -208,8 +208,8 @@ class RecordType(VHDLModel_RecordType, DOMMixin): @export class ProtectedType(VHDLModel_ProtectedType, DOMMixin): - def __init__(self, node: Iir, name: str, methods: Union[List, Iterator] = None): - super().__init__(name, methods) + def __init__(self, node: Iir, identifier: str, methods: Union[List, Iterator] = None): + super().__init__(identifier, methods) DOMMixin.__init__(self, node) @classmethod @@ -229,9 +229,9 @@ class ProtectedType(VHDLModel_ProtectedType, DOMMixin): @export class ProtectedTypeBody(VHDLModel_ProtectedTypeBody, DOMMixin): def __init__( - self, node: Iir, name: str, declaredItems: Union[List, Iterator] = None + self, node: Iir, identifier: str, declaredItems: Union[List, Iterator] = None ): - super().__init__(name, declaredItems) + super().__init__(identifier, declaredItems) DOMMixin.__init__(self, node) @classmethod @@ -250,8 +250,8 @@ class ProtectedTypeBody(VHDLModel_ProtectedTypeBody, DOMMixin): @export class AccessType(VHDLModel_AccessType, DOMMixin): - def __init__(self, node: Iir, name: str, designatedSubType: SubTypeOrSymbol): - super().__init__(name, designatedSubType) + def __init__(self, node: Iir, identifier: str, designatedSubType: SubTypeOrSymbol): + super().__init__(identifier, designatedSubType) DOMMixin.__init__(self, node) @classmethod @@ -270,8 +270,8 @@ class AccessType(VHDLModel_AccessType, DOMMixin): @export class FileType(VHDLModel_FileType, DOMMixin): - def __init__(self, node: Iir, name: str, designatedSubType: SubTypeOrSymbol): - super().__init__(name, designatedSubType) + def __init__(self, node: Iir, identifier: str, designatedSubType: SubTypeOrSymbol): + super().__init__(identifier, designatedSubType) DOMMixin.__init__(self, node) @classmethod diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index f7994b36d..98e17a5d0 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -160,7 +160,7 @@ class PrettyPrint: prefix = " " * level buffer.append( "{prefix}- Name: {name} at {file}:{line}:{column}".format( - name=entity.Name, + name=entity.Identifier, prefix=prefix, file=entity.Position.Filename.name, line=entity.Position.Line, @@ -189,7 +189,7 @@ class PrettyPrint: prefix = " " * level buffer.append( "{prefix}- Name: {name} at {file}:{line}:{column}".format( - name=architecture.Name, + name=architecture.Identifier, prefix=prefix, file=architecture.Position.Filename.name, line=architecture.Position.Line, @@ -212,7 +212,7 @@ class PrettyPrint: buffer = [] prefix = " " * level buffer.append( - "{prefix}- Component: {name}".format(name=component.Name, prefix=prefix) + "{prefix}- Component: {name}".format(name=component.Identifier, prefix=prefix) ) buffer.append("{prefix} Generics:".format(prefix=prefix)) for generic in component.GenericItems: @@ -228,7 +228,7 @@ class PrettyPrint: def formatPackage(self, package: Package, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}- Name: {name}".format(name=package.Name, prefix=prefix)) + buffer.append("{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix)) buffer.append("{prefix} Declared:".format(prefix=prefix)) for item in package.DeclaredItems: for line in self.formatDeclaredItems(item, level + 1): @@ -241,7 +241,7 @@ class PrettyPrint: ) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}- Name: {name}".format(name=package.Name, prefix=prefix)) + buffer.append("{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix)) buffer.append( "{prefix} Package: {name!s}".format( prefix=prefix, name=package.PackageReference @@ -260,7 +260,7 @@ class PrettyPrint: buffer = [] prefix = " " * level buffer.append( - "{prefix}- Name: {name}".format(name=packageBody.Name, prefix=prefix) + "{prefix}- Name: {name}".format(name=packageBody.Identifier, prefix=prefix) ) buffer.append("{prefix} Declared:".format(prefix=prefix)) for item in packageBody.DeclaredItems: @@ -275,7 +275,7 @@ class PrettyPrint: buffer = [] prefix = " " * level buffer.append( - "{prefix}- Name: {name}".format(name=configuration.Name, prefix=prefix) + "{prefix}- Name: {name}".format(name=configuration.Identifier, prefix=prefix) ) return buffer @@ -283,7 +283,7 @@ class PrettyPrint: def formatContext(self, context: Context, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}- Name: {name}".format(name=context.Name, prefix=prefix)) + buffer.append("{prefix}- Name: {name}".format(name=context.Identifier, prefix=prefix)) return buffer @@ -296,7 +296,7 @@ class PrettyPrint: return self.formatGenericType(generic, level) else: raise PrettyPrintException( - "Unhandled generic kind for generic '{name}'.".format(name=generic.Name) + "Unhandled generic kind for generic '{name}'.".format(name=generic.Identifier) ) def formatPort( @@ -306,7 +306,7 @@ class PrettyPrint: return self.formatPortSignal(port, level) else: raise PrettyPrintException( - "Unhandled port kind for port '{name}'.".format(name=port.Name) + "Unhandled port kind for port '{name}'.".format(name=port.Identifier) ) def formatGenericConstant( @@ -318,10 +318,10 @@ class PrettyPrint: buffer.append( "{prefix} - {name} : {mode!s} {subtypeindication}{initialValue}".format( prefix=prefix, - name=generic.Name, + name=generic.Identifier, mode=generic.Mode, subtypeindication=self.formatSubtypeIndication( - generic.SubType, "generic", generic.Name + generic.SubType, "generic", generic.Identifier ), initialValue=self.formatInitialValue(generic), ) @@ -338,7 +338,7 @@ class PrettyPrint: buffer.append( "{prefix} - type {name}".format( prefix=prefix, - name=generic.Name, + name=generic.Identifier, ) ) @@ -353,10 +353,10 @@ class PrettyPrint: buffer.append( "{prefix} - {name} : {mode!s} {subtypeindication}{initialValue}".format( prefix=prefix, - name=port.Name, + name=port.Identifier, mode=port.Mode, subtypeindication=self.formatSubtypeIndication( - port.SubType, "port", port.Name + port.SubType, "port", port.Identifier ), initialValue=self.formatInitialValue(port), ) @@ -372,9 +372,9 @@ class PrettyPrint: buffer.append( "{prefix}- constant {name} : {subtype} := {expr}".format( prefix=prefix, - name=item.Name, + name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "constant", item.Name + item.SubType, "constant", item.Identifier ), expr=str(item.DefaultExpression), ) @@ -383,9 +383,9 @@ class PrettyPrint: buffer.append( "{prefix}- shared variable {name} : {subtype}".format( prefix=prefix, - name=item.Name, + name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "shared variable", item.Name + item.SubType, "shared variable", item.Identifier ), ) ) @@ -393,9 +393,9 @@ class PrettyPrint: buffer.append( "{prefix}- signal {name} : {subtype}{initValue}".format( prefix=prefix, - name=item.Name, + name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "signal", item.Name + item.SubType, "signal", item.Identifier ), initValue=" := {expr}".format(expr=str(item.DefaultExpression)) if item.DefaultExpression is not None @@ -406,9 +406,9 @@ class PrettyPrint: buffer.append( "{prefix}- File {name} : {subtype}".format( prefix=prefix, - name=item.Name, + name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "file", item.Name + item.SubType, "file", item.Identifier ), ) ) @@ -420,27 +420,27 @@ class PrettyPrint: buffer.append( "{prefix}- subtype {name} is ?????".format( prefix=prefix, - name=item.Name, + name=item.Identifier, ) ) elif isinstance(item, Alias): buffer.append( "{prefix}- alias {name} is ?????".format( prefix=prefix, - name=item.Name, + name=item.Identifier, ) ) elif isinstance(item, Function): buffer.append( "{prefix}- function {name} return {returnType!s}".format( - prefix=prefix, name=item.Name, returnType=item.ReturnType + prefix=prefix, name=item.Identifier, returnType=item.ReturnType ) ) elif isinstance(item, Procedure): buffer.append( "{prefix}- procedure {name}".format( prefix=prefix, - name=item.Name, + name=item.Identifier, ) ) elif isinstance(item, Component): @@ -449,7 +449,7 @@ class PrettyPrint: elif isinstance(item, Attribute): buffer.append( "{prefix}- attribute {name} : {type!s}".format( - prefix=prefix, name=item.Name, type=item.SubType + prefix=prefix, name=item.Identifier, type=item.SubType ) ) elif isinstance(item, AttributeSpecification): @@ -469,7 +469,7 @@ class PrettyPrint: elif isinstance(item, PackageInstantiation): buffer.append( "{prefix}- package {name} is new {name2!s} generic map (.....)".format( - prefix=prefix, name=item.Name, name2=item.PackageReference + prefix=prefix, name=item.Identifier, name2=item.PackageReference ) ) else: @@ -482,7 +482,7 @@ class PrettyPrint: return buffer def formatType(self, item: BaseType) -> str: - result = "type {name} is ".format(name=item.Name) + result = "type {name} is ".format(name=item.Identifier) if isinstance(item, IncompleteType): result += "" elif isinstance(item, IntegerType): -- cgit v1.2.3 From c61eaa86a324db2dc1ee50004c1a505ae437b43d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:34:48 +0200 Subject: Added Allocations. --- pyGHDL/dom/Expression.py | 34 +++++++++++++++++++++++++++++++++- pyGHDL/dom/_Translate.py | 2 ++ 2 files changed, 35 insertions(+), 1 deletion(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 3dc1271f2..91ff19f12 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -73,6 +73,8 @@ from pyVHDLModel.VHDLModel import ( ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression, RotateRightExpression as VHDLModel_RotateRightExpression, RotateLeftExpression as VHDLModel_RotateLeftExpression, + SubtypeAllocation as VHDLModel_SubtypeAllocation, + QualifiedExpressionAllocation as VHDLModel_QualifiedExpressionAllocation, Aggregate as VHDLModel_Aggregate, Expression, AggregateElement, @@ -444,7 +446,37 @@ class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) subType = SimpleSubTypeSymbol(node, typeMarkName) operand = GetExpressionFromNode(nodes.Get_Expression(node)) - return cls(node, subType, operand) + return cls(node, subtype, operand) + + +@export +class SubtypeAllocation(VHDLModel_SubtypeAllocation, DOMMixin): + def __init__(self, node: Iir, subtype: Symbol): + super().__init__(subtype) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, node: Iir) -> "QualifiedExpressionAllocation": + from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode + + subtype = GetSubtypeIndicationFromNode(node, "allocation", "?") + + return cls(node, subtype) + + +@export +class QualifiedExpressionAllocation(VHDLModel_QualifiedExpressionAllocation, DOMMixin): + def __init__(self, node: Iir, qualifiedExpression: QualifiedExpression): + super().__init__(qualifiedExpression) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, node: Iir) -> "QualifiedExpressionAllocation": + from pyGHDL.dom._Translate import GetExpressionFromNode + + expression = GetExpressionFromNode(nodes.Get_Expression(node)) + + return cls(node, expression) @export diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 6cc993de7..77b0d31d3 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -412,6 +412,8 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Ror_Operator: RotateRightExpression, nodes.Iir_Kind.Qualified_Expression: QualifiedExpression, nodes.Iir_Kind.Aggregate: Aggregate, + nodes.Iir_Kind.Allocator_By_Subtype: SubtypeAllocation, + nodes.Iir_Kind.Allocator_By_Expression: QualifiedExpressionAllocation, } -- cgit v1.2.3 From ac702e68dd4287e1639c9f2efe4421cf1f3a0910 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:37:55 +0200 Subject: Added missing operators, especially matching operators. --- pyGHDL/dom/Expression.py | 78 +++++++++++++++++++++++++++++++++++++++++++----- pyGHDL/dom/_Translate.py | 20 ++++++++++++- 2 files changed, 90 insertions(+), 8 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 91ff19f12..a5af9afc4 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -30,12 +30,14 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ -from typing import List +from typing import List, Union from pydecor import export from pyGHDL.dom import DOMMixin, DOMException from pyVHDLModel.VHDLModel import ( + UnaryExpression as VHDLModel_UnaryExpression, + BinaryExpression as VHDLModel_BinaryExpression, InverseExpression as VHDLModel_InverseExpression, IdentityExpression as VHDLModel_IdentityExpression, NegationExpression as VHDLModel_NegationExpression, @@ -67,6 +69,12 @@ from pyVHDLModel.VHDLModel import ( LessEqualExpression as VHDLModel_LessEqualExpression, GreaterThanExpression as VHDLModel_GreaterThanExpression, GreaterEqualExpression as VHDLModel_GreaterEqualExpression, + MatchingEqualExpression as VHDLModel_MatchingEqualExpression, + MatchingUnequalExpression as VHDLModel_MatchingUnequalExpression, + MatchingLessThanExpression as VHDLModel_MatchingLessThanExpression, + MatchingLessEqualExpression as VHDLModel_MatchingLessEqualExpression, + MatchingGreaterThanExpression as VHDLModel_MatchingGreaterThanExpression, + MatchingGreaterEqualExpression as VHDLModel_MatchingGreaterEqualExpression, ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, @@ -101,7 +109,7 @@ __all__ = [] class _ParseUnaryExpressionMixin: @classmethod - def parse(cls, node: Iir): + def parse(cls, node: Iir) -> VHDLModel_UnaryExpression: from pyGHDL.dom._Translate import GetExpressionFromNode operand = GetExpressionFromNode(nodes.Get_Operand(node)) @@ -110,7 +118,7 @@ class _ParseUnaryExpressionMixin: class _ParseBinaryExpressionMixin: @classmethod - def parse(cls, node: Iir): + def parse(cls, node: Iir) -> VHDLModel_BinaryExpression: from pyGHDL.dom._Translate import GetExpressionFromNode left = GetExpressionFromNode(nodes.Get_Left(node)) @@ -163,7 +171,7 @@ class ParenthesisExpression( DOMMixin.__init__(self, node) @classmethod - def parse(cls, node: Iir): + def parse(cls, node: Iir) -> "ParenthesisExpression": from pyGHDL.dom._Translate import GetExpressionFromNode operand = GetExpressionFromNode(nodes.Get_Expression(node)) @@ -186,7 +194,9 @@ class FunctionCall(VHDLModel_FunctionCall, DOMMixin): class RangeExpression(VHDLModel_RangeExpression, DOMMixin): @classmethod - def parse(cls, node: Iir) -> "VHDLModel_RangeExpression": + def parse( + cls, node: Iir + ) -> Union["AscendingRangeExpression", "DescendingRangeExpression"]: from pyGHDL.dom._Translate import GetExpressionFromNode direction = nodes.Get_Direction(node) @@ -379,6 +389,60 @@ class GreaterEqualExpression( DOMMixin.__init__(self, node) +@export +class MatchingEqualExpression( + VHDLModel_MatchingEqualExpression, DOMMixin, _ParseBinaryExpressionMixin +): + def __init__(self, node: Iir, left: Expression, right: Expression): + super().__init__(left, right) + DOMMixin.__init__(self, node) + + +@export +class MatchingUnequalExpression( + VHDLModel_MatchingUnequalExpression, DOMMixin, _ParseBinaryExpressionMixin +): + def __init__(self, node: Iir, left: Expression, right: Expression): + super().__init__(left, right) + DOMMixin.__init__(self, node) + + +@export +class MatchingLessThanExpression( + VHDLModel_MatchingLessThanExpression, DOMMixin, _ParseBinaryExpressionMixin +): + def __init__(self, node: Iir, left: Expression, right: Expression): + super().__init__(left, right) + DOMMixin.__init__(self, node) + + +@export +class MatchingLessEqualExpression( + VHDLModel_MatchingLessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin +): + def __init__(self, node: Iir, left: Expression, right: Expression): + super().__init__(left, right) + DOMMixin.__init__(self, node) + + +@export +class MatchingGreaterThanExpression( + VHDLModel_MatchingGreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin +): + def __init__(self, node: Iir, left: Expression, right: Expression): + super().__init__(left, right) + DOMMixin.__init__(self, node) + + +@export +class MatchingGreaterEqualExpression( + VHDLModel_MatchingGreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin +): + def __init__(self, node: Iir, left: Expression, right: Expression): + super().__init__(left, right) + DOMMixin.__init__(self, node) + + @export class ShiftRightLogicExpression( VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin @@ -440,7 +504,7 @@ class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): DOMMixin.__init__(self, node) @classmethod - def parse(cls, node: Iir): + def parse(cls, node: Iir) -> "QualifiedExpression": from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) @@ -486,7 +550,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): DOMMixin.__init__(self, node) @classmethod - def parse(cls, node: Iir): + def parse(cls, node: Iir) -> "Aggregate": from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 77b0d31d3..89f25138f 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -126,6 +126,16 @@ from pyGHDL.dom.Expression import ( RotateLeftExpression, RotateRightExpression, RangeExpression, + QualifiedExpressionAllocation, + SubtypeAllocation, + IdentityExpression, + AbsoluteExpression, + MatchingGreaterEqualExpression, + MatchingEqualExpression, + MatchingUnequalExpression, + MatchingLessThanExpression, + MatchingLessEqualExpression, + MatchingGreaterThanExpression, ) from pyGHDL.dom.Subprogram import Function, Procedure from pyGHDL.dom.Misc import Alias @@ -380,7 +390,9 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Physical_Fp_Literal: PhysicalFloatingLiteral, nodes.Iir_Kind.Character_Literal: CharacterLiteral, nodes.Iir_Kind.String_Literal8: StringLiteral, + nodes.Iir_Kind.Identity_Operator: IdentityExpression, nodes.Iir_Kind.Negation_Operator: NegationExpression, + nodes.Iir_Kind.Absolute_Operator: AbsoluteExpression, nodes.Iir_Kind.Range_Expression: RangeExpression, nodes.Iir_Kind.Addition_Operator: AdditionExpression, nodes.Iir_Kind.Concatenation_Operator: ConcatenationExpression, @@ -403,7 +415,13 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Less_Than_Operator: LessThanExpression, nodes.Iir_Kind.Less_Than_Or_Equal_Operator: LessEqualExpression, nodes.Iir_Kind.Greater_Than_Operator: GreaterThanExpression, - nodes.Iir_Kind.Greater_Than_Or_Equal_Operator: GreaterEqualExpression, + nodes.Iir_Kind.Greater_Than_Or_Equal_Operator: MatchingGreaterEqualExpression, + nodes.Iir_Kind.Match_Equality_Operator: MatchingEqualExpression, + nodes.Iir_Kind.Match_Inequality_Operator: MatchingUnequalExpression, + nodes.Iir_Kind.Match_Less_Than_Operator: MatchingLessThanExpression, + nodes.Iir_Kind.Match_Less_Than_Or_Equal_Operator: MatchingLessEqualExpression, + nodes.Iir_Kind.Match_Greater_Than_Operator: MatchingGreaterThanExpression, + nodes.Iir_Kind.Match_Greater_Than_Or_Equal_Operator: MatchingGreaterEqualExpression, nodes.Iir_Kind.Sll_Operator: ShiftLeftLogicExpression, nodes.Iir_Kind.Srl_Operator: ShiftRightLogicExpression, nodes.Iir_Kind.Sla_Operator: ShiftLeftArithmeticExpression, -- cgit v1.2.3 From 87e356ef6c674393bba497019db13c90f2e8bd86 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:40:22 +0200 Subject: Reworked scalar types created from ranges. --- pyGHDL/dom/Type.py | 21 ++++++++++++--------- pyGHDL/dom/_Translate.py | 4 ++++ pyGHDL/dom/formatting/prettyprint.py | 4 +--- 3 files changed, 17 insertions(+), 12 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index ea4765ed1..3d388956b 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -46,8 +46,9 @@ from pyVHDLModel.VHDLModel import ( FileType as VHDLModel_FileType, ProtectedType as VHDLModel_ProtectedType, ProtectedTypeBody as VHDLModel_ProtectedTypeBody, - SubType as VHDLModel_SubType, - SubTypeOrSymbol, + Subtype as VHDLModel_Subtype, + SubtypeOrSymbol, + Name, ) from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir @@ -92,13 +93,10 @@ class EnumeratedType(VHDLModel_EnumeratedType, DOMMixin): @export class IntegerType(VHDLModel_IntegerType, DOMMixin): - def __init__(self, node: Iir, typeName: str, range: Range): - super().__init__(typeName) + def __init__(self, node: Iir, typeName: str, rng: Union[Range, "Name"]): + super().__init__(typeName, rng) DOMMixin.__init__(self, node) - self._leftBound = range.LeftBound - self._rightBound = range.RightBound - @export class PhysicalType(VHDLModel_PhysicalType, DOMMixin): @@ -106,14 +104,19 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): self, node: Iir, typeName: str, + rng: Union[Range, Name], primaryUnit: str, units: List[Tuple[str, PhysicalIntegerLiteral]], ): - super().__init__(typeName, primaryUnit, units) + super().__init__(typeName, rng, primaryUnit, units) DOMMixin.__init__(self, node) @classmethod def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "PhysicalType": + from pyGHDL.dom._Translate import GetRangeFromNode + + rng = GetRangeFromNode(nodes.Get_Range_Constraint(typeDefinitionNode)) + primaryUnit = nodes.Get_Primary_Unit(typeDefinitionNode) primaryUnitName = GetNameOfNode(primaryUnit) @@ -129,7 +132,7 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): units.append((secondaryUnitName, physicalLiteral)) - return cls(typeDefinitionNode, typeName, primaryUnitName, units) + return cls(typeDefinitionNode, typeName, rng, primaryUnitName, units) @export diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 89f25138f..1c97d403e 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -270,6 +270,10 @@ def GetAnonymousTypeFromNode(node: Iir) -> BaseType: r = GetRangeFromNode(typeDefinition) return IntegerType(node, typeName, r) + elif kind == nodes.Iir_Kind.Parenthesis_Name: + n = GetNameFromNode(typeDefinition) + + return IntegerType(node, typeName, n) elif kind == nodes.Iir_Kind.Physical_Type_Definition: return PhysicalType.parse(typeName, typeDefinition) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 98e17a5d0..9fb412d09 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -486,9 +486,7 @@ class PrettyPrint: if isinstance(item, IncompleteType): result += "" elif isinstance(item, IntegerType): - result += "range {left!s} to {right!s}".format( - left=item.LeftBound, right=item.RightBound - ) + result += "range {range!s}".format(range=item.Range) elif isinstance(item, EnumeratedType): result += "(........)" elif isinstance(item, PhysicalType): -- cgit v1.2.3 From 520f541c3a476bd91e0506c5fa9a3c5eaca5a842 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:41:30 +0200 Subject: Preparations for PSL. --- pyGHDL/dom/DesignUnit.py | 4 +- pyGHDL/dom/NonStandard.py | 13 ++++++ pyGHDL/dom/PSL.py | 112 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+), 2 deletions(-) create mode 100644 pyGHDL/dom/PSL.py (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 54816aef1..d5bf161fd 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -41,8 +41,6 @@ This module contains all DOM classes for VHDL's design units (:class:`context . +# +# SPDX-License-Identifier: GPL-2.0-or-later +# ============================================================================ + +""" +This module contains all DOM classes for VHDL's design units (:class:`context `, +:class:`architecture `, :class:`package `, +:class:`package body `, :class:`context ` and +:class:`configuration `. + + +""" +from pydecor import export + +from pyVHDLModel.PSLModel import ( + VerificationUnit as VHDLModel_VerificationUnit, + VerificationProperty as VHDLModel_VerificationProperty, + VerificationMode as VHDLModel_VerificationMode, +) + +from pyGHDL.libghdl._types import Iir +from pyGHDL.dom import DOMMixin +from pyGHDL.dom._Utils import GetNameOfNode + + +__all__ = [] + + +@export +class VerificationUnit(VHDLModel_VerificationUnit, DOMMixin): + def __init__( + self, + node: Iir, + identifier: str, + ): + super().__init__(identifier) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, vunitNode: Iir): + name = GetNameOfNode(vunitNode) + + # FIXME: needs an implementation + + return cls(vunitNode, name) + + +@export +class VerificationProperty(VHDLModel_VerificationProperty, DOMMixin): + def __init__( + self, + node: Iir, + identifier: str, + ): + super().__init__(identifier) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, vpropNode: Iir): + name = GetNameOfNode(vpropNode) + + # FIXME: needs an implementation + + return cls(vpropNode, name) + + +@export +class VerificationMode(VHDLModel_VerificationMode, DOMMixin): + def __init__( + self, + node: Iir, + identifier: str, + ): + super().__init__(identifier) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, vmodeNode: Iir): + name = GetNameOfNode(vmodeNode) + + # FIXME: needs an implementation + + return cls(vmodeNode, name) -- cgit v1.2.3 From 7f4ed5db5e0e9c0967000d50a4f3f14e88bf9dd7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:43:00 +0200 Subject: Renamed '[sS]ubType' to '[sS]ubtype'. --- pyGHDL/dom/Attribute.py | 16 ++++---- pyGHDL/dom/Expression.py | 10 ++--- pyGHDL/dom/InterfaceItem.py | 52 +++++++++++------------ pyGHDL/dom/Object.py | 64 ++++++++++++++--------------- pyGHDL/dom/Subprogram.py | 8 ++-- pyGHDL/dom/Symbol.py | 32 +++++++-------- pyGHDL/dom/Type.py | 62 +++++++++++++++------------- pyGHDL/dom/_Translate.py | 80 ++++++++++++++++++------------------ pyGHDL/dom/formatting/prettyprint.py | 60 ++++++++++++++++----------- 9 files changed, 200 insertions(+), 184 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py index 3fef7494c..62708da43 100644 --- a/pyGHDL/dom/Attribute.py +++ b/pyGHDL/dom/Attribute.py @@ -36,30 +36,30 @@ from pyVHDLModel.VHDLModel import ( Attribute as VHDLModel_Attribute, AttributeSpecification as VHDLModel_AttributeSpecification, Name, - SubTypeOrSymbol, + SubtypeOrSymbol, ) from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode from pyGHDL.dom._Translate import GetNameFromNode -from pyGHDL.dom.Symbol import SimpleSubTypeSymbol +from pyGHDL.dom.Symbol import SimpleSubtypeSymbol @export class Attribute(VHDLModel_Attribute, DOMMixin): - def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): - super().__init__(identifier, subType) + def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol): + super().__init__(identifier, subtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, attributeNode: Iir) -> "Attribute": name = GetNameOfNode(attributeNode) - subTypeMark = nodes.Get_Type_Mark(attributeNode) - subTypeName = GetNameOfNode(subTypeMark) + subtypeMark = nodes.Get_Type_Mark(attributeNode) + subtypeName = GetNameOfNode(subtypeMark) - subType = SimpleSubTypeSymbol(subTypeMark, subTypeName) - return cls(attributeNode, name, subType) + subtype = SimpleSubtypeSymbol(subtypeMark, subtypeName) + return cls(attributeNode, name, subtype) @export diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index a5af9afc4..972b86ced 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -86,7 +86,7 @@ from pyVHDLModel.VHDLModel import ( Aggregate as VHDLModel_Aggregate, Expression, AggregateElement, - SubTypeOrSymbol, + SubtypeOrSymbol, Symbol, ) @@ -94,7 +94,7 @@ from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import GetIirKindOfNode -from pyGHDL.dom.Symbol import SimpleSubTypeSymbol +from pyGHDL.dom.Symbol import SimpleSubtypeSymbol from pyGHDL.dom.Aggregates import ( OthersAggregateElement, SimpleAggregateElement, @@ -499,8 +499,8 @@ class RotateLeftExpression( @export class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): - def __init__(self, node: Iir, subType: SubTypeOrSymbol, operand: Expression): - super().__init__(subType, operand) + def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: Expression): + super().__init__(subtype, operand) DOMMixin.__init__(self, node) @classmethod @@ -508,7 +508,7 @@ class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) - subType = SimpleSubTypeSymbol(node, typeMarkName) + subtype = SimpleSubtypeSymbol(node, typeMarkName) operand = GetExpressionFromNode(nodes.Get_Expression(node)) return cls(node, subtype, operand) diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index 72f79d694..4ebea735a 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -44,7 +44,7 @@ from pyVHDLModel.VHDLModel import ( ParameterSignalInterfaceItem as VHDLModel_ParameterSignalInterfaceItem, ParameterFileInterfaceItem as VHDLModel_ParameterFileInterfaceItem, Mode, - SubTypeOrSymbol, + SubtypeOrSymbol, Expression, ) @@ -52,7 +52,7 @@ from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode, GetModeOfNode -from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode, GetExpressionFromNode +from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode __all__ = [] @@ -65,21 +65,21 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMi node: Iir, identifier: str, mode: Mode, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression, ): - super().__init__(identifier, mode, subType, defaultExpression) + super().__init__(identifier, mode, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, genericNode: Iir) -> "GenericConstantInterfaceItem": name = GetNameOfNode(genericNode) mode = GetModeOfNode(genericNode) - subTypeIndication = GetSubTypeIndicationFromNode(genericNode, "generic", name) + subtypeIndication = GetSubtypeIndicationFromNode(genericNode, "generic", name) default = nodes.Get_Default_Value(genericNode) value = GetExpressionFromNode(default) if default else None - return cls(genericNode, name, mode, subTypeIndication, value) + return cls(genericNode, name, mode, subtypeIndication, value) @export @@ -157,17 +157,17 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin): node: Iir, identifier: str, mode: Mode, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(identifier, mode, subType, defaultExpression) + super().__init__(identifier, mode, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, portNode: Iir) -> "PortSignalInterfaceItem": name = GetNameOfNode(portNode) mode = GetModeOfNode(portNode) - subTypeIndication = GetSubTypeIndicationFromNode(portNode, "port", name) + subtypeIndication = GetSubtypeIndicationFromNode(portNode, "port", name) defaultValue = nodes.Get_Default_Value(portNode) value = ( @@ -176,7 +176,7 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin): else None ) - return cls(portNode, name, mode, subTypeIndication, value) + return cls(portNode, name, mode, subtypeIndication, value) @export @@ -188,17 +188,17 @@ class ParameterConstantInterfaceItem( node: Iir, identifier: str, mode: Mode, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(identifier, mode, subType, defaultExpression) + super().__init__(identifier, mode, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, parameterNode: Iir) -> "ParameterConstantInterfaceItem": name = GetNameOfNode(parameterNode) mode = GetModeOfNode(parameterNode) - subTypeIndication = GetSubTypeIndicationFromNode( + subtypeIndication = GetSubtypeIndicationFromNode( parameterNode, "parameter", name ) @@ -209,7 +209,7 @@ class ParameterConstantInterfaceItem( else None ) - return cls(parameterNode, name, mode, subTypeIndication, value) + return cls(parameterNode, name, mode, subtypeIndication, value) @export @@ -221,17 +221,17 @@ class ParameterVariableInterfaceItem( node: Iir, identifier: str, mode: Mode, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(identifier, mode, subType, defaultExpression) + super().__init__(identifier, mode, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, parameterNode: Iir) -> "ParameterVariableInterfaceItem": name = GetNameOfNode(parameterNode) mode = GetModeOfNode(parameterNode) - subTypeIndication = GetSubTypeIndicationFromNode( + subtypeIndication = GetSubtypeIndicationFromNode( parameterNode, "parameter", name ) @@ -242,7 +242,7 @@ class ParameterVariableInterfaceItem( else None ) - return cls(parameterNode, name, mode, subTypeIndication, value) + return cls(parameterNode, name, mode, subtypeIndication, value) @export @@ -252,17 +252,17 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi node: Iir, identifier: str, mode: Mode, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression = None, ): - super().__init__(identifier, mode, subType, defaultExpression) + super().__init__(identifier, mode, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, parameterNode: Iir) -> "ParameterSignalInterfaceItem": name = GetNameOfNode(parameterNode) mode = GetModeOfNode(parameterNode) - subTypeIndication = GetSubTypeIndicationFromNode( + subtypeIndication = GetSubtypeIndicationFromNode( parameterNode, "parameter", name ) @@ -273,7 +273,7 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi else None ) - return cls(parameterNode, name, mode, subTypeIndication, value) + return cls(parameterNode, name, mode, subtypeIndication, value) @export @@ -282,16 +282,16 @@ class ParameterFileInterfaceItem(VHDLModel_ParameterFileInterfaceItem, DOMMixin) self, node: Iir, identifier: str, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, ): - super().__init__(identifier, subType) + super().__init__(identifier, subtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, parameterNode: Iir) -> "ParameterFileInterfaceItem": name = GetNameOfNode(parameterNode) - subTypeIndication = GetSubTypeIndicationFromNode( + subtypeIndication = GetSubtypeIndicationFromNode( parameterNode, "parameter", name ) - return cls(parameterNode, name, subTypeIndication) + return cls(parameterNode, name, subtypeIndication) diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py index 97bfdaa82..d25acb587 100644 --- a/pyGHDL/dom/Object.py +++ b/pyGHDL/dom/Object.py @@ -43,7 +43,7 @@ from pyVHDLModel.VHDLModel import ( Signal as VHDLModel_Signal, File as VHDLModel_File, Expression, - SubTypeOrSymbol, + SubtypeOrSymbol, ) from pyGHDL.libghdl.vhdl import nodes @@ -59,46 +59,46 @@ class Constant(VHDLModel_Constant, DOMMixin): self, node: Iir, identifier: str, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression, ): - super().__init__(identifier, subType, defaultExpression) + super().__init__(identifier, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, constantNode: Iir) -> Union["Constant", "DeferredConstant"]: from pyGHDL.dom._Translate import ( - GetSubTypeIndicationFromNode, + GetSubtypeIndicationFromNode, GetExpressionFromNode, ) name = GetNameOfNode(constantNode) - subTypeIndication = GetSubTypeIndicationFromNode(constantNode, "constant", name) + subtypeIndication = GetSubtypeIndicationFromNode(constantNode, "constant", name) defaultValue = nodes.Get_Default_Value(constantNode) if defaultValue != nodes.Null_Iir: defaultExpression = GetExpressionFromNode(defaultValue) - return cls(constantNode, name, subTypeIndication, defaultExpression) + return cls(constantNode, name, subtypeIndication, defaultExpression) else: - return DeferredConstant(constantNode, name, subTypeIndication) + return DeferredConstant(constantNode, name, subtypeIndication) @export class DeferredConstant(VHDLModel_DeferredConstant, DOMMixin): - def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): - super().__init__(identifier, subType) + def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol): + super().__init__(identifier, subtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, constantNode: Iir) -> "DeferredConstant": - from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode + from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode name = GetNameOfNode(constantNode) - subTypeIndication = GetSubTypeIndicationFromNode( + subtypeIndication = GetSubtypeIndicationFromNode( constantNode, "deferred constant", name ) - return cls(constantNode, name, subTypeIndication) + return cls(constantNode, name, subtypeIndication) @export @@ -107,43 +107,43 @@ class Variable(VHDLModel_Variable, DOMMixin): self, node: Iir, identifier: str, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression, ): - super().__init__(identifier, subType, defaultExpression) + super().__init__(identifier, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, variableNode: Iir) -> "Variable": from pyGHDL.dom._Translate import ( - GetSubTypeIndicationFromNode, + GetSubtypeIndicationFromNode, GetExpressionFromNode, ) name = GetNameOfNode(variableNode) - subTypeIndication = GetSubTypeIndicationFromNode(variableNode, "variable", name) + subtypeIndication = GetSubtypeIndicationFromNode(variableNode, "variable", name) defaultValue = nodes.Get_Default_Value(variableNode) defaultExpression = None if defaultValue != nodes.Null_Iir: defaultExpression = GetExpressionFromNode(defaultValue) - return cls(variableNode, name, subTypeIndication, defaultExpression) + return cls(variableNode, name, subtypeIndication, defaultExpression) @export class SharedVariable(VHDLModel_SharedVariable, DOMMixin): - def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): - super().__init__(identifier, subType) + def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol): + super().__init__(identifier, subtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, variableNode: Iir) -> "SharedVariable": - from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode + from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode name = GetNameOfNode(variableNode) - subTypeIndication = GetSubTypeIndicationFromNode(variableNode, "variable", name) + subtypeIndication = GetSubtypeIndicationFromNode(variableNode, "variable", name) - return cls(variableNode, name, subTypeIndication) + return cls(variableNode, name, subtypeIndication) @export @@ -152,40 +152,40 @@ class Signal(VHDLModel_Signal, DOMMixin): self, node: Iir, identifier: str, - subType: SubTypeOrSymbol, + subtype: SubtypeOrSymbol, defaultExpression: Expression, ): - super().__init__(identifier, subType, defaultExpression) + super().__init__(identifier, subtype, defaultExpression) DOMMixin.__init__(self, node) @classmethod def parse(cls, signalNode: Iir) -> "Signal": from pyGHDL.dom._Translate import ( - GetSubTypeIndicationFromNode, + GetSubtypeIndicationFromNode, GetExpressionFromNode, ) name = GetNameOfNode(signalNode) - subTypeIndication = GetSubTypeIndicationFromNode(signalNode, "signal", name) + subtypeIndication = GetSubtypeIndicationFromNode(signalNode, "signal", name) default = nodes.Get_Default_Value(signalNode) defaultExpression = GetExpressionFromNode(default) if default else None - return cls(signalNode, name, subTypeIndication, defaultExpression) + return cls(signalNode, name, subtypeIndication, defaultExpression) @export class File(VHDLModel_File, DOMMixin): - def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): - super().__init__(identifier, subType) + def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol): + super().__init__(identifier, subtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, fileNode: Iir) -> "File": - from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode + from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode name = GetNameOfNode(fileNode) - subTypeIndication = GetSubTypeIndicationFromNode(fileNode, "file", name) + subtypeIndication = GetSubtypeIndicationFromNode(fileNode, "file", name) # FIXME: handle file open stuff - return cls(fileNode, name, subTypeIndication) + return cls(fileNode, name, subtypeIndication) diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py index 42e3c7d79..e8e5ebbb4 100644 --- a/pyGHDL/dom/Subprogram.py +++ b/pyGHDL/dom/Subprogram.py @@ -37,7 +37,7 @@ from pydecor import export from pyVHDLModel.VHDLModel import ( Function as VHDLModel_Function, Procedure as VHDLModel_Procedure, - SubTypeOrSymbol, + SubtypeOrSymbol, GenericInterfaceItem, ParameterInterfaceItem, ) @@ -45,7 +45,7 @@ from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode -from pyGHDL.dom.Symbol import SimpleSubTypeSymbol +from pyGHDL.dom.Symbol import SimpleSubtypeSymbol @export @@ -54,7 +54,7 @@ class Function(VHDLModel_Function, DOMMixin): self, node: Iir, functionName: str, - returnType: SubTypeOrSymbol, + returnType: SubtypeOrSymbol, genericItems: List[GenericInterfaceItem] = None, parameterItems: List[ParameterInterfaceItem] = None, ): @@ -84,7 +84,7 @@ class Function(VHDLModel_Function, DOMMixin): returnType = nodes.Get_Return_Type_Mark(functionNode) returnTypeName = GetNameOfNode(returnType) - returnTypeSymbol = SimpleSubTypeSymbol(returnType, returnTypeName) + returnTypeSymbol = SimpleSubtypeSymbol(returnType, returnTypeName) return cls(functionNode, functionName, returnTypeSymbol, generics, parameters) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index be8dd362e..3597f2572 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -36,9 +36,9 @@ from pydecor import export from pyVHDLModel.VHDLModel import ( EntitySymbol as VHDLModel_EntitySymbol, - SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, - ConstrainedScalarSubTypeSymbol as VHDLModel_ConstrainedScalarSubTypeSymbol, - ConstrainedCompositeSubTypeSymbol as VHDLModel_ConstrainedCompositeSubTypeSymbol, + SimpleSubtypeSymbol as VHDLModel_SimpleSubtypeSymbol, + ConstrainedScalarSubtypeSymbol as VHDLModel_ConstrainedScalarSubtypeSymbol, + ConstrainedCompositeSubtypeSymbol as VHDLModel_ConstrainedCompositeSubtypeSymbol, SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol, IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol, Constraint, @@ -60,21 +60,21 @@ class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin): @export -class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol, DOMMixin): - def __init__(self, node: Iir, subTypeName: Name): - if isinstance(subTypeName, (List, Iterator)): - subTypeName = ".".join(subTypeName) +class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin): + def __init__(self, node: Iir, subtypeName: Name): + if isinstance(subtypeName, (List, Iterator)): + subtypeName = ".".join(subtypeName) - super().__init__(subTypeName=subTypeName) + super().__init__(subtypeName=subtypeName) DOMMixin.__init__(self, node) @export -class ConstrainedScalarSubTypeSymbol( - VHDLModel_ConstrainedScalarSubTypeSymbol, DOMMixin +class ConstrainedScalarSubtypeSymbol( + VHDLModel_ConstrainedScalarSubtypeSymbol, DOMMixin ): - def __init__(self, node: Iir, subTypeName: Name, rng: Range = None): - super().__init__(subTypeName, rng) + def __init__(self, node: Iir, subtypeName: Name, rng: Range = None): + super().__init__(subtypeName, rng) DOMMixin.__init__(self, node) @classmethod @@ -83,13 +83,13 @@ class ConstrainedScalarSubTypeSymbol( @export -class ConstrainedCompositeSubTypeSymbol( - VHDLModel_ConstrainedCompositeSubTypeSymbol, DOMMixin +class ConstrainedCompositeSubtypeSymbol( + VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin ): def __init__( - self, node: Iir, subTypeName: Name, constraints: List[Constraint] = None + self, node: Iir, subtypeName: Name, constraints: List[Constraint] = None ): - super().__init__(subTypeName, constraints) + super().__init__(subtypeName, constraints) DOMMixin.__init__(self, node) @classmethod diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index 3d388956b..efe32afc2 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -55,7 +55,7 @@ from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, DOMException from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode -from pyGHDL.dom.Symbol import SimpleSubTypeSymbol +from pyGHDL.dom.Symbol import SimpleSubtypeSymbol from pyGHDL.dom.Literal import EnumerationLiteral, PhysicalIntegerLiteral from pyGHDL.dom.Range import Range from pyGHDL.dom.Subprogram import Function, Procedure @@ -138,16 +138,16 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): @export class ArrayType(VHDLModel_ArrayType, DOMMixin): def __init__( - self, node: Iir, identifier: str, indices: List, elementSubType: SubTypeOrSymbol + self, node: Iir, identifier: str, indices: List, elementSubtype: SubtypeOrSymbol ): - super().__init__(identifier, indices, elementSubType) + super().__init__(identifier, indices, elementSubtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "ArrayType": from pyGHDL.dom._Translate import ( GetSimpleTypeFromNode, - GetSubTypeIndicationFromIndicationNode, + GetSubtypeIndicationFromIndicationNode, ) indices = [] @@ -155,8 +155,8 @@ class ArrayType(VHDLModel_ArrayType, DOMMixin): for index in utils.flist_iter(indexDefinitions): indexKind = GetIirKindOfNode(index) if indexKind == nodes.Iir_Kind.Simple_Name: - indexSubType = GetSimpleTypeFromNode(index) - indices.append(indexSubType) + indexSubtype = GetSimpleTypeFromNode(index) + indices.append(indexSubtype) else: raise DOMException( "Unknown kind '{kind}' for an index in the array definition of `{typeName}`.".format( @@ -164,28 +164,28 @@ class ArrayType(VHDLModel_ArrayType, DOMMixin): ) ) - elementSubTypeIndication = nodes.Get_Element_Subtype_Indication( + elementSubtypeIndication = nodes.Get_Element_Subtype_Indication( typeDefinitionNode ) - elementSubType = GetSubTypeIndicationFromIndicationNode( - elementSubTypeIndication, "array declaration", typeName + elementSubtype = GetSubtypeIndicationFromIndicationNode( + elementSubtypeIndication, "array declaration", typeName ) - return cls(typeDefinitionNode, typeName, indices, elementSubType) + return cls(typeDefinitionNode, typeName, indices, elementSubtype) @export class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin): - def __init__(self, node: Iir, identifier: str, subType: SubTypeOrSymbol): - super().__init__(identifier, subType) + def __init__(self, node: Iir, identifier: str, subtype: SubtypeOrSymbol): + super().__init__(identifier, subtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, elementDeclarationNode: Iir) -> "RecordTypeElement": - from pyGHDL.dom._Translate import GetSubTypeIndicationFromNode + from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode elementName = GetNameOfNode(elementDeclarationNode) - elementType = GetSubTypeIndicationFromNode( + elementType = GetSubtypeIndicationFromNode( elementDeclarationNode, "record element", elementName ) @@ -194,7 +194,9 @@ class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin): @export class RecordType(VHDLModel_RecordType, DOMMixin): - def __init__(self, node: Iir, identifier: str, elements: List[RecordTypeElement] = None): + def __init__( + self, node: Iir, identifier: str, elements: List[RecordTypeElement] = None + ): super().__init__(identifier, elements) DOMMixin.__init__(self, node) @@ -211,7 +213,9 @@ class RecordType(VHDLModel_RecordType, DOMMixin): @export class ProtectedType(VHDLModel_ProtectedType, DOMMixin): - def __init__(self, node: Iir, identifier: str, methods: Union[List, Iterator] = None): + def __init__( + self, node: Iir, identifier: str, methods: Union[List, Iterator] = None + ): super().__init__(identifier, methods) DOMMixin.__init__(self, node) @@ -253,44 +257,44 @@ class ProtectedTypeBody(VHDLModel_ProtectedTypeBody, DOMMixin): @export class AccessType(VHDLModel_AccessType, DOMMixin): - def __init__(self, node: Iir, identifier: str, designatedSubType: SubTypeOrSymbol): - super().__init__(identifier, designatedSubType) + def __init__(self, node: Iir, identifier: str, designatedSubtype: SubtypeOrSymbol): + super().__init__(identifier, designatedSubtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "AccessType": - from pyGHDL.dom._Translate import GetSubTypeIndicationFromIndicationNode + from pyGHDL.dom._Translate import GetSubtypeIndicationFromIndicationNode designatedSubtypeIndication = nodes.Get_Designated_Subtype_Indication( typeDefinitionNode ) - designatedSubType = GetSubTypeIndicationFromIndicationNode( + designatedSubtype = GetSubtypeIndicationFromIndicationNode( designatedSubtypeIndication, "access type", typeName ) - return cls(typeDefinitionNode, typeName, designatedSubType) + return cls(typeDefinitionNode, typeName, designatedSubtype) @export class FileType(VHDLModel_FileType, DOMMixin): - def __init__(self, node: Iir, identifier: str, designatedSubType: SubTypeOrSymbol): - super().__init__(identifier, designatedSubType) + def __init__(self, node: Iir, identifier: str, designatedSubtype: SubtypeOrSymbol): + super().__init__(identifier, designatedSubtype) DOMMixin.__init__(self, node) @classmethod def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "FileType": - designatedSubTypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode) - designatedSubTypeName = GetNameOfNode(designatedSubTypeMark) - designatedSubType = SimpleSubTypeSymbol( - typeDefinitionNode, designatedSubTypeName + designatedSubtypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode) + designatedSubtypeName = GetNameOfNode(designatedSubtypeMark) + designatedSubtype = SimpleSubtypeSymbol( + typeDefinitionNode, designatedSubtypeName ) - return cls(typeDefinitionNode, typeName, designatedSubType) + return cls(typeDefinitionNode, typeName, designatedSubtype) @export -class SubType(VHDLModel_SubType, DOMMixin): +class Subtype(VHDLModel_Subtype, DOMMixin): def __init__(self, node: Iir, subtypeName: str): super().__init__(subtypeName) DOMMixin.__init__(self, node) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 1c97d403e..8229755f3 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -40,7 +40,7 @@ from pyVHDLModel.VHDLModel import ( Constraint, Direction, Expression, - SubTypeOrSymbol, + SubtypeOrSymbol, BaseType, GenericInterfaceItem, PortInterfaceItem, @@ -65,14 +65,14 @@ from pyGHDL.dom.Names import ( ) from pyGHDL.dom.Symbol import ( SimpleObjectOrFunctionCallSymbol, - SimpleSubTypeSymbol, - ConstrainedCompositeSubTypeSymbol, + SimpleSubtypeSymbol, + ConstrainedCompositeSubtypeSymbol, IndexedObjectOrFunctionCallSymbol, - ConstrainedScalarSubTypeSymbol, + ConstrainedScalarSubtypeSymbol, ) from pyGHDL.dom.Type import ( IntegerType, - SubType, + Subtype, ArrayType, RecordType, EnumeratedType, @@ -192,11 +192,11 @@ def GetAssociations(node: Iir) -> List: @export def GetArrayConstraintsFromSubtypeIndication( - subTypeIndication: Iir, + subtypeIndication: Iir, ) -> List[Constraint]: constraints = [] for constraint in utils.flist_iter( - nodes.Get_Index_Constraint_List(subTypeIndication) + nodes.Get_Index_Constraint_List(subtypeIndication) ): constraintKind = GetIirKindOfNode(constraint) if constraintKind == nodes.Iir_Kind.Range_Expression: @@ -214,7 +214,7 @@ def GetArrayConstraintsFromSubtypeIndication( "Unknown constraint kind '{kind}' for constraint '{constraint}' in subtype indication '{indication}' at {file}:{line}:{column}.".format( kind=constraintKind.name, constraint=constraint, - indication=subTypeIndication, + indication=subtypeIndication, file=position.Filename, line=position.Line, column=position.Column, @@ -295,35 +295,35 @@ def GetAnonymousTypeFromNode(node: Iir) -> BaseType: @export -def GetSubTypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubTypeOrSymbol: - subTypeIndicationNode = nodes.Get_Subtype_Indication(node) - # if subTypeIndicationNode is nodes.Null_Iir: +def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubtypeOrSymbol: + subtypeIndicationNode = nodes.Get_Subtype_Indication(node) + # if subtypeIndicationNode is nodes.Null_Iir: # return None - return GetSubTypeIndicationFromIndicationNode(subTypeIndicationNode, entity, name) + return GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode, entity, name) @export -def GetSubTypeIndicationFromIndicationNode( - subTypeIndicationNode: Iir, entity: str, name: str -) -> SubTypeOrSymbol: - if subTypeIndicationNode is nodes.Null_Iir: +def GetSubtypeIndicationFromIndicationNode( + subtypeIndicationNode: Iir, entity: str, name: str +) -> SubtypeOrSymbol: + if subtypeIndicationNode is nodes.Null_Iir: print( "[NOT IMPLEMENTED]: Unhandled multiple declarations for {entity} '{name}'.".format( entity=entity, name=name ) ) return None - kind = GetIirKindOfNode(subTypeIndicationNode) + kind = GetIirKindOfNode(subtypeIndicationNode) if kind in ( nodes.Iir_Kind.Simple_Name, nodes.Iir_Kind.Selected_Name, nodes.Iir_Kind.Attribute_Name, ): - return GetSimpleTypeFromNode(subTypeIndicationNode) + return GetSimpleTypeFromNode(subtypeIndicationNode) elif kind == nodes.Iir_Kind.Subtype_Definition: - return GetScalarConstrainedSubTypeFromNode(subTypeIndicationNode) + return GetScalarConstrainedSubtypeFromNode(subtypeIndicationNode) elif kind == nodes.Iir_Kind.Array_Subtype_Definition: - return GetCompositeConstrainedSubTypeFromNode(subTypeIndicationNode) + return GetCompositeConstrainedSubtypeFromNode(subtypeIndicationNode) else: raise DOMException( "Unknown kind '{kind}' for an subtype indication in a {entity} of `{name}`.".format( @@ -333,40 +333,40 @@ def GetSubTypeIndicationFromIndicationNode( @export -def GetSimpleTypeFromNode(subTypeIndicationNode: Iir) -> SimpleSubTypeSymbol: - subTypeName = GetNameFromNode(subTypeIndicationNode) - return SimpleSubTypeSymbol(subTypeIndicationNode, subTypeName) +def GetSimpleTypeFromNode(subtypeIndicationNode: Iir) -> SimpleSubtypeSymbol: + subtypeName = GetNameFromNode(subtypeIndicationNode) + return SimpleSubtypeSymbol(subtypeIndicationNode, subtypeName) @export -def GetScalarConstrainedSubTypeFromNode( - subTypeIndicationNode: Iir, -) -> ConstrainedScalarSubTypeSymbol: - typeMark = nodes.Get_Subtype_Type_Mark(subTypeIndicationNode) +def GetScalarConstrainedSubtypeFromNode( + subtypeIndicationNode: Iir, +) -> ConstrainedScalarSubtypeSymbol: + typeMark = nodes.Get_Subtype_Type_Mark(subtypeIndicationNode) typeMarkName = GetNameOfNode(typeMark) - rangeConstraint = nodes.Get_Range_Constraint(subTypeIndicationNode) + rangeConstraint = nodes.Get_Range_Constraint(subtypeIndicationNode) r = GetRangeFromNode(rangeConstraint) - return ConstrainedScalarSubTypeSymbol(subTypeIndicationNode, typeMarkName, r) + return ConstrainedScalarSubtypeSymbol(subtypeIndicationNode, typeMarkName, r) @export -def GetCompositeConstrainedSubTypeFromNode( - subTypeIndicationNode: Iir, -) -> ConstrainedCompositeSubTypeSymbol: - typeMark = nodes.Get_Subtype_Type_Mark(subTypeIndicationNode) +def GetCompositeConstrainedSubtypeFromNode( + subtypeIndicationNode: Iir, +) -> ConstrainedCompositeSubtypeSymbol: + typeMark = nodes.Get_Subtype_Type_Mark(subtypeIndicationNode) typeMarkName = GetNameOfNode(typeMark) - constraints = GetArrayConstraintsFromSubtypeIndication(subTypeIndicationNode) - return ConstrainedCompositeSubTypeSymbol( - subTypeIndicationNode, typeMarkName, constraints + constraints = GetArrayConstraintsFromSubtypeIndication(subtypeIndicationNode) + return ConstrainedCompositeSubtypeSymbol( + subtypeIndicationNode, typeMarkName, constraints ) @export -def GetSubTypeFromNode(subTypeNode: Iir) -> SubTypeOrSymbol: - subTypeName = GetNameOfNode(subTypeNode) +def GetSubtypeFromNode(subtypeNode: Iir) -> SubtypeOrSymbol: + subtypeName = GetNameOfNode(subtypeNode) - return SubType(subTypeNode, subTypeName) + return Subtype(subtypeNode, subtypeName) @export @@ -595,7 +595,7 @@ def GetDeclaredItemsFromChainedNodes( yield GetAnonymousTypeFromNode(item) elif kind == nodes.Iir_Kind.Subtype_Declaration: - yield GetSubTypeFromNode(item) + yield GetSubtypeFromNode(item) elif kind == nodes.Iir_Kind.Function_Declaration: yield Function.parse(item) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 9fb412d09..4eef043f5 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -7,7 +7,7 @@ from pyGHDL.dom.Misc import Alias from pyGHDL.dom.Subprogram import Procedure from pyGHDL.dom.Type import ( IntegerType, - SubType, + Subtype, ArrayType, RecordType, AccessType, @@ -48,8 +48,8 @@ from pyGHDL.dom.InterfaceItem import ( GenericTypeInterfaceItem, ) from pyGHDL.dom.Symbol import ( - SimpleSubTypeSymbol, - ConstrainedCompositeSubTypeSymbol, + SimpleSubtypeSymbol, + ConstrainedCompositeSubtypeSymbol, ) @@ -212,7 +212,9 @@ class PrettyPrint: buffer = [] prefix = " " * level buffer.append( - "{prefix}- Component: {name}".format(name=component.Identifier, prefix=prefix) + "{prefix}- Component: {name}".format( + name=component.Identifier, prefix=prefix + ) ) buffer.append("{prefix} Generics:".format(prefix=prefix)) for generic in component.GenericItems: @@ -228,7 +230,9 @@ class PrettyPrint: def formatPackage(self, package: Package, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix)) + buffer.append( + "{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix) + ) buffer.append("{prefix} Declared:".format(prefix=prefix)) for item in package.DeclaredItems: for line in self.formatDeclaredItems(item, level + 1): @@ -241,7 +245,9 @@ class PrettyPrint: ) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix)) + buffer.append( + "{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix) + ) buffer.append( "{prefix} Package: {name!s}".format( prefix=prefix, name=package.PackageReference @@ -275,7 +281,9 @@ class PrettyPrint: buffer = [] prefix = " " * level buffer.append( - "{prefix}- Name: {name}".format(name=configuration.Identifier, prefix=prefix) + "{prefix}- Name: {name}".format( + name=configuration.Identifier, prefix=prefix + ) ) return buffer @@ -283,7 +291,9 @@ class PrettyPrint: def formatContext(self, context: Context, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append("{prefix}- Name: {name}".format(name=context.Identifier, prefix=prefix)) + buffer.append( + "{prefix}- Name: {name}".format(name=context.Identifier, prefix=prefix) + ) return buffer @@ -296,7 +306,9 @@ class PrettyPrint: return self.formatGenericType(generic, level) else: raise PrettyPrintException( - "Unhandled generic kind for generic '{name}'.".format(name=generic.Identifier) + "Unhandled generic kind for generic '{name}'.".format( + name=generic.Identifier + ) ) def formatPort( @@ -321,7 +333,7 @@ class PrettyPrint: name=generic.Identifier, mode=generic.Mode, subtypeindication=self.formatSubtypeIndication( - generic.SubType, "generic", generic.Identifier + generic.Subtype, "generic", generic.Identifier ), initialValue=self.formatInitialValue(generic), ) @@ -356,7 +368,7 @@ class PrettyPrint: name=port.Identifier, mode=port.Mode, subtypeindication=self.formatSubtypeIndication( - port.SubType, "port", port.Identifier + port.Subtype, "port", port.Identifier ), initialValue=self.formatInitialValue(port), ) @@ -374,7 +386,7 @@ class PrettyPrint: prefix=prefix, name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "constant", item.Identifier + item.Subtype, "constant", item.Identifier ), expr=str(item.DefaultExpression), ) @@ -385,7 +397,7 @@ class PrettyPrint: prefix=prefix, name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "shared variable", item.Identifier + item.Subtype, "shared variable", item.Identifier ), ) ) @@ -395,7 +407,7 @@ class PrettyPrint: prefix=prefix, name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "signal", item.Identifier + item.Subtype, "signal", item.Identifier ), initValue=" := {expr}".format(expr=str(item.DefaultExpression)) if item.DefaultExpression is not None @@ -408,7 +420,7 @@ class PrettyPrint: prefix=prefix, name=item.Identifier, subtype=self.formatSubtypeIndication( - item.SubType, "file", item.Identifier + item.Subtype, "file", item.Identifier ), ) ) @@ -416,7 +428,7 @@ class PrettyPrint: buffer.append( "{prefix}- {type}".format(prefix=prefix, type=self.formatType(item)) ) - elif isinstance(item, SubType): + elif isinstance(item, Subtype): buffer.append( "{prefix}- subtype {name} is ?????".format( prefix=prefix, @@ -449,7 +461,7 @@ class PrettyPrint: elif isinstance(item, Attribute): buffer.append( "{prefix}- attribute {name} : {type!s}".format( - prefix=prefix, name=item.Identifier, type=item.SubType + prefix=prefix, name=item.Identifier, type=item.Subtype ) ) elif isinstance(item, AttributeSpecification): @@ -510,21 +522,21 @@ class PrettyPrint: return result - def formatSubtypeIndication(self, subTypeIndication, entity: str, name: str) -> str: - if isinstance(subTypeIndication, SimpleSubTypeSymbol): - return "{type}".format(type=subTypeIndication.SymbolName) - elif isinstance(subTypeIndication, ConstrainedCompositeSubTypeSymbol): + def formatSubtypeIndication(self, subtypeIndication, entity: str, name: str) -> str: + if isinstance(subtypeIndication, SimpleSubtypeSymbol): + return "{type}".format(type=subtypeIndication.SymbolName) + elif isinstance(subtypeIndication, ConstrainedCompositeSubtypeSymbol): constraints = [] - for constraint in subTypeIndication.Constraints: + for constraint in subtypeIndication.Constraints: constraints.append(str(constraint)) return "{type}({constraints})".format( - type=subTypeIndication.SymbolName, constraints=", ".join(constraints) + type=subtypeIndication.SymbolName, constraints=", ".join(constraints) ) else: raise PrettyPrintException( "Unhandled subtype kind '{type}' for {entity} '{name}'.".format( - type=subTypeIndication.__class__.__name__, entity=entity, name=name + type=subtypeIndication.__class__.__name__, entity=entity, name=name ) ) -- cgit v1.2.3 From 6acaf4b6baba21f8eca7520f518c62ffd75abd04 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 19:10:33 +0200 Subject: Minor changes. --- pyGHDL/dom/_Translate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 8229755f3..fc8f86b42 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -270,7 +270,7 @@ def GetAnonymousTypeFromNode(node: Iir) -> BaseType: r = GetRangeFromNode(typeDefinition) return IntegerType(node, typeName, r) - elif kind == nodes.Iir_Kind.Parenthesis_Name: + elif kind in (nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name): n = GetNameFromNode(typeDefinition) return IntegerType(node, typeName, n) -- cgit v1.2.3 From 03f5a6cd6f88aef6c6580f471905403056313f05 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 30 Jun 2021 12:20:54 +0200 Subject: Exchanged sides in asserts to the understanding of pytests actual vs. expected order. --- pyGHDL/dom/Range.py | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Range.py b/pyGHDL/dom/Range.py index d091be1c6..ce8dfbc40 100644 --- a/pyGHDL/dom/Range.py +++ b/pyGHDL/dom/Range.py @@ -44,9 +44,4 @@ __all__ = [] @export class Range(VHDLModel_Range): - def __init__(self, left: Expression, right: Expression, direction: Direction): - super().__init__() - - self._leftBound = left - self._rightBound = right - self._direction = direction + pass -- cgit v1.2.3 From 12a6518bf4d2e41664210b77a5416eca0d1dc7af Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 30 Jun 2021 13:03:00 +0200 Subject: Extended attribute specification. --- pyGHDL/dom/Attribute.py | 86 +++++++++++++++++++++++++++++++++++++++++++----- pyGHDL/dom/_Translate.py | 5 ++- 2 files changed, 79 insertions(+), 12 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py index 62708da43..270f8feb3 100644 --- a/pyGHDL/dom/Attribute.py +++ b/pyGHDL/dom/Attribute.py @@ -30,6 +30,8 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from typing import List + from pydecor import export from pyVHDLModel.VHDLModel import ( @@ -37,12 +39,16 @@ from pyVHDLModel.VHDLModel import ( AttributeSpecification as VHDLModel_AttributeSpecification, Name, SubtypeOrSymbol, + EntityClass, ) +from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes -from pyGHDL.dom import DOMMixin +from pyGHDL.libghdl.vhdl.tokens import Tok +from pyGHDL.dom import DOMMixin, Position, DOMException, Expression from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode -from pyGHDL.dom._Translate import GetNameFromNode +from pyGHDL.dom._Translate import GetNameFromNode, GetExpressionFromNode +from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Symbol import SimpleSubtypeSymbol @@ -62,10 +68,42 @@ class Attribute(VHDLModel_Attribute, DOMMixin): return cls(attributeNode, name, subtype) +_TOKEN_TRANSLATION = { + Tok.Entity: EntityClass.Entity, + Tok.Architecture: EntityClass.Architecture, + Tok.Configuration: EntityClass.Configuration, + Tok.Procedure: EntityClass.Procedure, + Tok.Function: EntityClass.Function, + Tok.Package: EntityClass.Package, + Tok.Type: EntityClass.Type, + Tok.Subtype: EntityClass.Subtype, + Tok.Constant: EntityClass.Constant, + Tok.Signal: EntityClass.Signal, + Tok.Variable: EntityClass.Variable, + Tok.Component: EntityClass.Component, + Tok.Label: EntityClass.Label, + Tok.Literal: EntityClass.Literal, + Tok.Units: EntityClass.Units, + Tok.Group: EntityClass.Group, + Tok.File: EntityClass.File, + Tok.Property: EntityClass.Property, + Tok.Sequence: EntityClass.Sequence, + # Tok.View: EntityClass.View, + Tok.Others: EntityClass.Others, +} + + @export class AttributeSpecification(VHDLModel_AttributeSpecification, DOMMixin): - def __init__(self, node: Iir, attribute: Name): - super().__init__(attribute) + def __init__( + self, + node: Iir, + identifiers: List[Name], + attribute: Name, + entityClass: EntityClass, + expression: Expression, + ): + super().__init__(identifiers, attribute, entityClass, expression) DOMMixin.__init__(self, node) @classmethod @@ -73,11 +111,41 @@ class AttributeSpecification(VHDLModel_AttributeSpecification, DOMMixin): attributeDesignator = nodes.Get_Attribute_Designator(attributeNode) attributeName = GetNameFromNode(attributeDesignator) - # FIXME: needs an implementation + names = [] entityNameList = nodes.Get_Entity_Name_List(attributeNode) - enlk = GetIirKindOfNode(entityNameList) + for name in utils.flist_iter(entityNameList): + nameKind = GetIirKindOfNode(name) + if nameKind == nodes.Iir_Kind.Simple_Name: + names.append(SimpleName(name, GetNameOfNode(name))) + elif nameKind == nodes.Iir_Kind.Signature: + print("[NOT IMPLEMENTED] Signature name in attribute specifications.") + else: + position = Position.parse(name) + raise DOMException( + "Unknown name kind '{kind}' in attribute specification '{attr}' at {file}:{line}:{column}.".format( + kind=nameKind.name, + attr=attributeNode, + file=position.Filename, + line=position.Line, + column=position.Column, + ) + ) + + entityClassToken = nodes.Get_Entity_Class(attributeNode) + try: + entityClass = _TOKEN_TRANSLATION[entityClassToken] + except KeyError: + position = Position.parse(attributeNode) + raise DOMException( + "Unknown token '{token}' in attribute specification for entity class '{entityClass}' at {file}:{line}:{column}.".format( + token=entityClassToken.name, + entityClass=attributeNode, + file=position.Filename, + line=position.Line, + column=position.Column, + ) + ) - entityClass = nodes.Get_Entity_Class(attributeNode) - eck = GetIirKindOfNode(entityClass) + expression = GetExpressionFromNode(nodes.Get_Expression(attributeNode)) - return cls(attributeNode, attributeName) + return cls(attributeNode, names, attributeName, entityClass, expression) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index fc8f86b42..4e9515767 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -448,9 +448,8 @@ def GetExpressionFromNode(node: Iir) -> Expression: except KeyError: position = Position.parse(node) raise DOMException( - "Unknown expression kind '{kindName}'({kind}) in expression '{expr}' at {file}:{line}:{column}.".format( - kind=kind, - kindName=kind.name, + "Unknown expression kind '{kind}' in expression '{expr}' at {file}:{line}:{column}.".format( + kind=kind.name, expr=node, file=position.Filename, line=position.Line, -- cgit v1.2.3 From 301dea333ec3e28e95a43b1a4af569ebbedd6ab9 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 30 Jun 2021 13:52:30 +0200 Subject: Added package declarations inside of declarations. Added PSL Default clock (dummy). Added Disconnect specification (dummy). --- pyGHDL/dom/PSL.py | 21 +++++++++++++++++++++ pyGHDL/dom/_Translate.py | 11 +++++++++++ pyGHDL/dom/formatting/prettyprint.py | 13 +++++++++++++ 3 files changed, 45 insertions(+) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py index dd859e5b3..6c4ba76b3 100644 --- a/pyGHDL/dom/PSL.py +++ b/pyGHDL/dom/PSL.py @@ -39,12 +39,14 @@ This module contains all DOM classes for VHDL's design units (:class:`context Date: Wed, 30 Jun 2021 23:38:41 +0200 Subject: Fixed bug in OthersAggregateElement. --- pyGHDL/dom/Aggregates.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py index 8edd037a1..87bc44360 100644 --- a/pyGHDL/dom/Aggregates.py +++ b/pyGHDL/dom/Aggregates.py @@ -88,7 +88,5 @@ class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin): @export class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin): def __init__(self, node: Iir, expression: Expression): - super().__init__() + super().__init__(expression) DOMMixin.__init__(self, node) - - self._expression = expression -- cgit v1.2.3 From ae51fcf65f195e065987f379410d3f68c14f4a2b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 2 Jul 2021 00:32:38 +0200 Subject: Changed dependency files. Fixed a typo. --- pyGHDL/dom/requirements.txt | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 pyGHDL/dom/requirements.txt (limited to 'pyGHDL/dom') diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt new file mode 100644 index 000000000..66e3025ae --- /dev/null +++ b/pyGHDL/dom/requirements.txt @@ -0,0 +1,4 @@ +-r ../libghdl/requirements.txt + +pyVHDLModel==0.11.1 +#https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel -- cgit v1.2.3