From de44ee29acb01edfb429eb88d96f0bb904adefd0 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 27 Jul 2021 18:48:08 +0200 Subject: Changed List to Iterable. Parse instantiations. Some SimpleName fixes. --- pyGHDL/dom/Concurrent.py | 118 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 pyGHDL/dom/Concurrent.py (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py new file mode 100644 index 000000000..80417c07b --- /dev/null +++ b/pyGHDL/dom/Concurrent.py @@ -0,0 +1,118 @@ +# ============================================================================= +# ____ _ _ ____ _ _ +# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___ +# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \ +# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | | +# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_| +# |_| |___/ +# ============================================================================= +# Authors: +# Patrick Lehmann +# +# Package module: DOM: Concurrent statements. +# +# License: +# ============================================================================ +# Copyright (C) 2019-2021 Tristan Gingold +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# SPDX-License-Identifier: GPL-2.0-or-later +# ============================================================================ +from typing import Iterable + +from pydecor import export + +from pyVHDLModel.SyntaxModel import ( + ConcurrentBlockStatement as VHDLModel_ConcurrentBlockStatement, + ComponentInstantiation as VHDLModel_ComponentInstantiation, + EntityInstantiation as VHDLModel_EntityInstantiation, + ConfigurationInstantiation as VHDLModel_ConfigurationInstantiation, + PortInterfaceItem, + ConcurrentStatement, +) + +from pyGHDL.libghdl import Iir +from pyGHDL.libghdl.vhdl import nodes +from pyGHDL.dom import DOMMixin +from pyGHDL.dom.Symbol import EntitySymbol + + +@export +class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): + def __init__(self, node: Iir, componentName: str): + super().__init__(componentName) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, instantiationNode: Iir) -> "ComponentInstantiation": + componentName = "" + + return cls(instantiationNode, componentName) + + +@export +class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): + def __init__(self, node: Iir, entityName: EntitySymbol): + super().__init__(entityName) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, instantiationNode: Iir) -> "EntityInstantiation": + entityName = "" + + return cls(instantiationNode, entityName) + + +@export +class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin): + def __init__(self, node: Iir, configurationName: str): + super().__init__(configurationName) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, instantiationNode: Iir) -> "ConfigurationInstantiation": + configurationName = "" + + return cls(instantiationNode, configurationName) + + +@export +class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): + def __init__( + self, + node: Iir, + label: str, + # portItems: Iterable[PortInterfaceItem] = None, + declaredItems: Iterable = None, + bodyItems: Iterable["ConcurrentStatement"] = None, + ): + super().__init__(label, None, declaredItems, bodyItems) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, blockNode: Iir, label: str) -> "ConcurrentBlockStatement": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + ) + + declaredItems = GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(blockNode), "block", label + ) + bodyItems = GetStatementsFromChainedNodes( + nodes.Get_Concurrent_Statement_Chain(blockNode), "block", label + ) + + return cls(blockNode, label, declaredItems, bodyItems) -- cgit v1.2.3 From 20b636decb9c502891fbf5f9a15cf8e7126904a5 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 28 Jul 2021 09:00:03 +0200 Subject: Handle instantiations 1/2. --- pyGHDL/dom/Concurrent.py | 48 ++++++++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 18 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 80417c07b..2698054e5 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -39,53 +39,65 @@ from pyVHDLModel.SyntaxModel import ( ComponentInstantiation as VHDLModel_ComponentInstantiation, EntityInstantiation as VHDLModel_EntityInstantiation, ConfigurationInstantiation as VHDLModel_ConfigurationInstantiation, - PortInterfaceItem, - ConcurrentStatement, + ConcurrentStatement, Name, ) from pyGHDL.libghdl import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin -from pyGHDL.dom.Symbol import EntitySymbol +from pyGHDL.dom._Utils import GetNameOfNode @export class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): - def __init__(self, node: Iir, componentName: str): - super().__init__(componentName) + def __init__(self, node: Iir, label: str, componentName: Name): + super().__init__(label, componentName) DOMMixin.__init__(self, node) @classmethod - def parse(cls, instantiationNode: Iir) -> "ComponentInstantiation": - componentName = "" + def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation": + from pyGHDL.dom._Translate import GetNameFromNode - return cls(instantiationNode, componentName) + componentName = GetNameFromNode(instantiatedUnit) + + return cls(instantiationNode, label, componentName) @export class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): - def __init__(self, node: Iir, entityName: EntitySymbol): - super().__init__(entityName) + def __init__(self, node: Iir, label: str, entityName: Name, architectureName: Name = None): + super().__init__(label, entityName, architectureName) DOMMixin.__init__(self, node) @classmethod - def parse(cls, instantiationNode: Iir) -> "EntityInstantiation": - entityName = "" + def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": + from pyGHDL.dom._Translate import GetNameFromNode + + entityId = nodes.Get_Entity_Name(instantiatedUnit) + entityName = GetNameFromNode(entityId) - return cls(instantiationNode, entityName) + architectureName = None + architectureId = nodes.Get_Architecture(instantiatedUnit) + if architectureId != nodes.Null_Iir: + architectureName = GetNameOfNode(architectureId) + + return cls(instantiationNode, label, entityName, architectureName) @export class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin): - def __init__(self, node: Iir, configurationName: str): - super().__init__(configurationName) + def __init__(self, node: Iir, label: str, configurationName: Name): + super().__init__(label, configurationName) DOMMixin.__init__(self, node) @classmethod - def parse(cls, instantiationNode: Iir) -> "ConfigurationInstantiation": - configurationName = "" + def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation": + from pyGHDL.dom._Translate import GetNameFromNode + + configurationId = nodes.Get_Configuration_Name(instantiatedUnit) + configurationName = GetNameFromNode(configurationId) - return cls(instantiationNode, configurationName) + return cls(instantiationNode, label, configurationName) @export -- cgit v1.2.3 From 50f65e4255f62e662d781d01f395c029426c1529 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 28 Jul 2021 23:52:31 +0200 Subject: More handling of concurrent statements. --- pyGHDL/dom/Concurrent.py | 171 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 156 insertions(+), 15 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 2698054e5..d4e7cf6ff 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -35,42 +35,63 @@ from typing import Iterable from pydecor import export from pyVHDLModel.SyntaxModel import ( - ConcurrentBlockStatement as VHDLModel_ConcurrentBlockStatement, ComponentInstantiation as VHDLModel_ComponentInstantiation, EntityInstantiation as VHDLModel_EntityInstantiation, ConfigurationInstantiation as VHDLModel_ConfigurationInstantiation, - ConcurrentStatement, Name, + ConcurrentBlockStatement as VHDLModel_ConcurrentBlockStatement, + ProcessStatement as VHDLModel_ProcessStatement, + IfGenerateBranch as VHDLModel_IfGenerateBranch, + IfGenerateStatement as VHDLModel_IfGenerateStatement, + CaseGenerateStatement as VHDLModel_CaseGenerateStatement, + ForGenerateStatement as VHDLModel_ForGenerateStatement, + ConcurrentStatement, + Name, + SequentialStatement, + IfGenerateBranch, ) from pyGHDL.libghdl import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin -from pyGHDL.dom._Utils import GetNameOfNode +from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode @export class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): - def __init__(self, node: Iir, label: str, componentName: Name): + def __init__(self, instantiationNode: Iir, label: str, componentName: Name): super().__init__(label, componentName) - DOMMixin.__init__(self, node) + DOMMixin.__init__(self, instantiationNode) @classmethod - def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation": + def parse( + cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str + ) -> "ComponentInstantiation": from pyGHDL.dom._Translate import GetNameFromNode componentName = GetNameFromNode(instantiatedUnit) + # TODO: get mapped generics + # TODO: get mapped ports + return cls(instantiationNode, label, componentName) @export class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): - def __init__(self, node: Iir, label: str, entityName: Name, architectureName: Name = None): + def __init__( + self, + instantiationNode: Iir, + label: str, + entityName: Name, + architectureName: Name = None, + ): super().__init__(label, entityName, architectureName) - DOMMixin.__init__(self, node) + DOMMixin.__init__(self, instantiationNode) @classmethod - def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": + def parse( + cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str + ) -> "EntityInstantiation": from pyGHDL.dom._Translate import GetNameFromNode entityId = nodes.Get_Entity_Name(instantiatedUnit) @@ -81,22 +102,30 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): if architectureId != nodes.Null_Iir: architectureName = GetNameOfNode(architectureId) + # TODO: get mapped generics + # TODO: get mapped ports + return cls(instantiationNode, label, entityName, architectureName) @export class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin): - def __init__(self, node: Iir, label: str, configurationName: Name): + def __init__(self, instantiationNode: Iir, label: str, configurationName: Name): super().__init__(label, configurationName) - DOMMixin.__init__(self, node) + DOMMixin.__init__(self, instantiationNode) @classmethod - def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation": + def parse( + cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str + ) -> "ConfigurationInstantiation": from pyGHDL.dom._Translate import GetNameFromNode configurationId = nodes.Get_Configuration_Name(instantiatedUnit) configurationName = GetNameFromNode(configurationId) + # TODO: get mapped generics + # TODO: get mapped ports + return cls(instantiationNode, label, configurationName) @@ -104,14 +133,13 @@ class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin) class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): def __init__( self, - node: Iir, + blockNode: Iir, label: str, - # portItems: Iterable[PortInterfaceItem] = None, declaredItems: Iterable = None, bodyItems: Iterable["ConcurrentStatement"] = None, ): super().__init__(label, None, declaredItems, bodyItems) - DOMMixin.__init__(self, node) + DOMMixin.__init__(self, blockNode) @classmethod def parse(cls, blockNode: Iir, label: str) -> "ConcurrentBlockStatement": @@ -128,3 +156,116 @@ class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): ) return cls(blockNode, label, declaredItems, bodyItems) + + +@export +class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): + def __init__( + self, + processNode: Iir, + label: str = None, + declaredItems: Iterable = None, + statements: Iterable[SequentialStatement] = None, + sensitivityList: Iterable[Name] = None, + ): + super().__init__(label, declaredItems, statements, sensitivityList) + DOMMixin.__init__(self, processNode) + + @classmethod + def parse( + cls, processNode: Iir, label: str, hasSensitivityList: bool + ) -> "ProcessStatement": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + ) + + # TODO: get sensitivity list + # TODO: get declared items + # TODO: get sequential statements + + declaredItems = None + statements = None + sensitivityList = None + + if hasSensitivityList: + pass + + return cls(processNode, label, declaredItems, statements, sensitivityList) + + +@export +class IfGenerateBranch(VHDLModel_IfGenerateBranch): + def __init__( + self, + branchNode: Iir, + alternativeLabel: str = None, + declaredItems: Iterable = None, + statements: Iterable[ConcurrentStatement] = None, + ): + super().__init__(declaredItems, statements) + DOMMixin.__init__(self, branchNode) + + +@export +class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): + def __init__(self, generateNode: Iir, label: str, ifBranch: IfGenerateBranch): + super().__init__(label, ifBranch) + DOMMixin.__init__(self, generateNode) + + @classmethod + def parse(cls, generateNode: Iir, label: str) -> "IfGenerateStatement": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + ) + + # TODO: get branches + # TODO: get declared items + # TODO: get concurrent statements + + body = nodes.Get_Generate_Statement_Body(generateNode) + alternativeLabelId = nodes.Get_Alternative_Label(body) + alternativeLabel = "" + + declarationChain = nodes.Get_Declaration_Chain(body) + declaredItems = GetDeclaredItemsFromChainedNodes( + declarationChain, "if-generate", label + ) + + statementChain = nodes.Get_Concurrent_Statement_Chain(body) + statements = GetStatementsFromChainedNodes(statementChain, "if-generate", label) + + ifBranch = IfGenerateBranch(body, alternativeLabel, declaredItems, statements) + + return cls(generateNode, label, ifBranch) + + +@export +class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): + def __init__(self, generateNode: Iir, label: str): + super().__init__(label) + DOMMixin.__init__(self, generateNode) + + @classmethod + def parse(cls, generateNode: Iir, label: str) -> "CaseGenerateStatement": + # TODO: get choices + # TODO: get declared items + # TODO: get concurrent statements + + return cls(generateNode, label) + + +@export +class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): + def __init__(self, generateNode: Iir, label: str): + super().__init__(label) + DOMMixin.__init__(self, generateNode) + + @classmethod + def parse(cls, generateNode: Iir, label: str) -> "ForGenerateStatement": + # TODO: get index and range + # TODO: get declared items + # TODO: get concurrent statements + + return cls(generateNode, label) -- cgit v1.2.3 From cfd625ab0a3d4df24bae77ed6143c44a53f26f49 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 29 Jul 2021 09:00:11 +0200 Subject: Moved parsing into IfGenerateBranch. --- pyGHDL/dom/Concurrent.py | 50 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 37 insertions(+), 13 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index d4e7cf6ff..c9a67f1e1 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -48,6 +48,7 @@ from pyVHDLModel.SyntaxModel import ( Name, SequentialStatement, IfGenerateBranch, + Expression, ) from pyGHDL.libghdl import Iir @@ -199,13 +200,40 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): def __init__( self, branchNode: Iir, + condition: Expression, alternativeLabel: str = None, declaredItems: Iterable = None, statements: Iterable[ConcurrentStatement] = None, ): - super().__init__(declaredItems, statements) + super().__init__(condition, declaredItems, statements) DOMMixin.__init__(self, branchNode) + @classmethod + def parse(cls, generateNode: Iir) -> "IfGenerateBranch": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + GetExpressionFromNode, + ) + + condition = GetExpressionFromNode(nodes.Get_Condition(generateNode)) + body = nodes.Get_Generate_Statement_Body(generateNode) + + alternativeLabelId = nodes.Get_Alternative_Label(body) + alternativeLabel = "" + + declarationChain = nodes.Get_Declaration_Chain(body) + declaredItems = GetDeclaredItemsFromChainedNodes( + declarationChain, "if-generate branch", alternativeLabel + ) + + statementChain = nodes.Get_Concurrent_Statement_Chain(body) + statements = GetStatementsFromChainedNodes( + statementChain, "if-generate branch", alternativeLabel + ) + + return cls(body, condition, alternativeLabel, declaredItems, statements) + @export class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): @@ -218,25 +246,21 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetStatementsFromChainedNodes, + GetExpressionFromNode, ) # TODO: get branches # TODO: get declared items # TODO: get concurrent statements - body = nodes.Get_Generate_Statement_Body(generateNode) - alternativeLabelId = nodes.Get_Alternative_Label(body) - alternativeLabel = "" - - declarationChain = nodes.Get_Declaration_Chain(body) - declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "if-generate", label - ) - - statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetStatementsFromChainedNodes(statementChain, "if-generate", label) + print(generateNode, GetIirKindOfNode(generateNode)) + ifBranch = IfGenerateBranch.parse(generateNode) - ifBranch = IfGenerateBranch(body, alternativeLabel, declaredItems, statements) + elseClause = generateNode + while ( + elseClause := nodes.Get_Generate_Else_Clause(elseClause) + ) != nodes.Null_Iir: + print(elseClause, GetIirKindOfNode(elseClause)) return cls(generateNode, label, ifBranch) -- cgit v1.2.3 From 2a571db9fecf39cc593b0a5666a540ef5cdc39fc Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 2 Aug 2021 03:30:53 +0200 Subject: Disabled Python 3.8 syntax. --- pyGHDL/dom/Concurrent.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index c9a67f1e1..6b07ff3ae 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -44,10 +44,9 @@ from pyVHDLModel.SyntaxModel import ( IfGenerateStatement as VHDLModel_IfGenerateStatement, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, - ConcurrentStatement, Name, + ConcurrentStatement, SequentialStatement, - IfGenerateBranch, Expression, ) @@ -256,12 +255,15 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): print(generateNode, GetIirKindOfNode(generateNode)) ifBranch = IfGenerateBranch.parse(generateNode) - elseClause = generateNode - while ( - elseClause := nodes.Get_Generate_Else_Clause(elseClause) - ) != nodes.Null_Iir: +# Python 3.8 syntax +# elseClause = generateNode +# while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: + elseClause = nodes.Get_Generate_Else_Clause(generateNode) + while elseClause != nodes.Null_Iir: print(elseClause, GetIirKindOfNode(elseClause)) + elseClause = nodes.Get_Generate_Else_Clause(elseClause) + return cls(generateNode, label, ifBranch) -- cgit v1.2.3 From 407f07a7b3100020bb9f5dbe5863c0b8b45cdd9d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 2 Aug 2021 11:52:48 +0200 Subject: Added handling of simple concurrent statements. --- pyGHDL/dom/Concurrent.py | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 6b07ff3ae..f57f4fa49 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -44,6 +44,7 @@ from pyVHDLModel.SyntaxModel import ( IfGenerateStatement as VHDLModel_IfGenerateStatement, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, + ConcurrentSignalAssignment as VHDLModel_ConcurrentSignalAssignment, Name, ConcurrentStatement, SequentialStatement, @@ -255,9 +256,9 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): print(generateNode, GetIirKindOfNode(generateNode)) ifBranch = IfGenerateBranch.parse(generateNode) -# Python 3.8 syntax -# elseClause = generateNode -# while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: + # Python 3.8 syntax + # elseClause = generateNode + # while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: elseClause = nodes.Get_Generate_Else_Clause(generateNode) while elseClause != nodes.Null_Iir: print(elseClause, GetIirKindOfNode(elseClause)) @@ -295,3 +296,34 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): # TODO: get concurrent statements return cls(generateNode, label) + + +@export +class ConcurrentSimpleSignalAssignment( + VHDLModel_ConcurrentSimpleSignalAssignment, DOMMixin +): + def __init__( + self, + assignmentNode: Iir, + target: Name, + expression: Expression, + label: str = None, + ): + super().__init__(target, expression, label) + DOMMixin.__init__(self, assignmentNode) + + @classmethod + def parse( + cls, assignmentNode: Iir, label: str + ) -> "ConcurrentSimpleSignalAssignment": + from pyGHDL.dom._Translate import GetNameFromNode + + target = nodes.Get_Target(assignmentNode) + targetName = GetNameFromNode(target) + + waveform = nodes.Get_Waveform_Chain(assignmentNode) + + # TODO: translate waveforms to series of "expressions". + expression = None + + return cls(assignmentNode, targetName, expression, label) -- cgit v1.2.3 From c80c2e02dda356e3eb00ae6a097ff62c0f08fc79 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 6 Aug 2021 20:11:33 +0200 Subject: Renamed to ConcurrentSimpleSignalAssignment. --- pyGHDL/dom/Concurrent.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index f57f4fa49..ab30f9176 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -44,7 +44,7 @@ from pyVHDLModel.SyntaxModel import ( IfGenerateStatement as VHDLModel_IfGenerateStatement, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, - ConcurrentSignalAssignment as VHDLModel_ConcurrentSignalAssignment, + ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment, Name, ConcurrentStatement, SequentialStatement, -- cgit v1.2.3 From 91392f7951f9a60f50d20c594e3b9c978a4104bc Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 00:39:05 +0200 Subject: Renamed BodyItems to Statements. --- pyGHDL/dom/Concurrent.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index ab30f9176..76ebd12a4 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -137,9 +137,9 @@ class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): blockNode: Iir, label: str, declaredItems: Iterable = None, - bodyItems: Iterable["ConcurrentStatement"] = None, + statements: Iterable["ConcurrentStatement"] = None, ): - super().__init__(label, None, declaredItems, bodyItems) + super().__init__(label, None, declaredItems, statements) DOMMixin.__init__(self, blockNode) @classmethod @@ -152,11 +152,11 @@ class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): declaredItems = GetDeclaredItemsFromChainedNodes( nodes.Get_Declaration_Chain(blockNode), "block", label ) - bodyItems = GetStatementsFromChainedNodes( + statements = GetStatementsFromChainedNodes( nodes.Get_Concurrent_Statement_Chain(blockNode), "block", label ) - return cls(blockNode, label, declaredItems, bodyItems) + return cls(blockNode, label, declaredItems, statements) @export -- cgit v1.2.3 From c5411e01a4ca454e8ffbe0a1d92b7bfd2c7d2217 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 00:40:16 +0200 Subject: More for generate statements. --- pyGHDL/dom/Concurrent.py | 91 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 86 insertions(+), 5 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 76ebd12a4..4e4240dbf 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -41,6 +41,8 @@ from pyVHDLModel.SyntaxModel import ( ConcurrentBlockStatement as VHDLModel_ConcurrentBlockStatement, ProcessStatement as VHDLModel_ProcessStatement, IfGenerateBranch as VHDLModel_IfGenerateBranch, + ElsifGenerateBranch as VHDLModel_ElsifGenerateBranch, + ElseGenerateBranch as VHDLModel_ElseGenerateBranch, IfGenerateStatement as VHDLModel_IfGenerateStatement, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, @@ -201,11 +203,11 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): self, branchNode: Iir, condition: Expression, - alternativeLabel: str = None, declaredItems: Iterable = None, statements: Iterable[ConcurrentStatement] = None, + alternativeLabel: str = None, ): - super().__init__(condition, declaredItems, statements) + super().__init__(condition, declaredItems, statements, alternativeLabel) DOMMixin.__init__(self, branchNode) @classmethod @@ -232,7 +234,85 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): statementChain, "if-generate branch", alternativeLabel ) - return cls(body, condition, alternativeLabel, declaredItems, statements) + return cls(body, condition, declaredItems, statements, alternativeLabel) + + +@export +class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): + def __init__( + self, + branchNode: Iir, + condition: Expression, + declaredItems: Iterable = None, + statements: Iterable[ConcurrentStatement] = None, + alternativeLabel: str = None, + ): + super().__init__(condition, declaredItems, statements, alternativeLabel) + DOMMixin.__init__(self, branchNode) + + @classmethod + def parse(cls, generateNode: Iir) -> "ElsifGenerateBranch": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + GetExpressionFromNode, + ) + + condition = GetExpressionFromNode(nodes.Get_Condition(generateNode)) + body = nodes.Get_Generate_Statement_Body(generateNode) + + alternativeLabelId = nodes.Get_Alternative_Label(body) + alternativeLabel = "" + + declarationChain = nodes.Get_Declaration_Chain(body) + declaredItems = GetDeclaredItemsFromChainedNodes( + declarationChain, "if-generate branch", alternativeLabel + ) + + statementChain = nodes.Get_Concurrent_Statement_Chain(body) + statements = GetStatementsFromChainedNodes( + statementChain, "if-generate branch", alternativeLabel + ) + + return cls(body, condition, declaredItems, statements, alternativeLabel) + + +@export +class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): + def __init__( + self, + branchNode: Iir, + declaredItems: Iterable = None, + statements: Iterable[ConcurrentStatement] = None, + alternativeLabel: str = None, + ): + super().__init__(declaredItems, statements, alternativeLabel) + DOMMixin.__init__(self, branchNode) + + @classmethod + def parse(cls, generateNode: Iir) -> "ElseGenerateBranch": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + GetExpressionFromNode, + ) + + body = nodes.Get_Generate_Statement_Body(generateNode) + + alternativeLabelId = nodes.Get_Alternative_Label(body) + alternativeLabel = "" + + declarationChain = nodes.Get_Declaration_Chain(body) + declaredItems = GetDeclaredItemsFromChainedNodes( + declarationChain, "if-generate branch", alternativeLabel + ) + + statementChain = nodes.Get_Concurrent_Statement_Chain(body) + statements = GetStatementsFromChainedNodes( + statementChain, "if-generate branch", alternativeLabel + ) + + return cls(body, declaredItems, statements, alternativeLabel) @export @@ -253,7 +333,7 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): # TODO: get declared items # TODO: get concurrent statements - print(generateNode, GetIirKindOfNode(generateNode)) + print("if branch", generateNode, GetIirKindOfNode(generateNode)) ifBranch = IfGenerateBranch.parse(generateNode) # Python 3.8 syntax @@ -261,7 +341,8 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): # while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: elseClause = nodes.Get_Generate_Else_Clause(generateNode) while elseClause != nodes.Null_Iir: - print(elseClause, GetIirKindOfNode(elseClause)) + print("els(if) branch", elseClause, GetIirKindOfNode(elseClause)) + ifBranch = ElsifGenerateBranch.parse(generateNode) elseClause = nodes.Get_Generate_Else_Clause(elseClause) -- cgit v1.2.3 From 92c3b2d6cf5835e0aa048a12dcc1e80b36990a4b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 00:40:45 +0200 Subject: Handle assignments (target and kind). --- pyGHDL/dom/Concurrent.py | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 4e4240dbf..990fc32c7 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -46,6 +46,7 @@ from pyVHDLModel.SyntaxModel import ( IfGenerateStatement as VHDLModel_IfGenerateStatement, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, + WaveformElement as VHDLModel_WaveformElement, ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment, Name, ConcurrentStatement, @@ -379,6 +380,19 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): return cls(generateNode, label) +@export +class WaveformElement( + VHDLModel_WaveformElement, DOMMixin +): + def __init__( + self, + waveformNode: Iir, + expression: Expression, + after: Expression + ): + super().__init__(expression, after) + DOMMixin.__init__(self, waveformNode) + @export class ConcurrentSimpleSignalAssignment( VHDLModel_ConcurrentSimpleSignalAssignment, DOMMixin @@ -386,11 +400,11 @@ class ConcurrentSimpleSignalAssignment( def __init__( self, assignmentNode: Iir, + label: str, target: Name, - expression: Expression, - label: str = None, + waveform: Iterable[WaveformElement], ): - super().__init__(target, expression, label) + super().__init__(label, target, waveform) DOMMixin.__init__(self, assignmentNode) @classmethod @@ -405,6 +419,6 @@ class ConcurrentSimpleSignalAssignment( waveform = nodes.Get_Waveform_Chain(assignmentNode) # TODO: translate waveforms to series of "expressions". - expression = None + expression = [None] - return cls(assignmentNode, targetName, expression, label) + return cls(assignmentNode, label, targetName, expression) -- cgit v1.2.3 From 3f31acc7304b03996f045f39b9e1130a4ffdc330 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 02:55:48 +0200 Subject: Improved pretty-printing for hierarchy. --- pyGHDL/dom/Concurrent.py | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 990fc32c7..69ae8bdea 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -318,8 +318,15 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): @export class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): - def __init__(self, generateNode: Iir, label: str, ifBranch: IfGenerateBranch): - super().__init__(label, ifBranch) + def __init__( + self, + generateNode: Iir, + label: str, + ifBranch: IfGenerateBranch, + elsifBranches: Iterable[ElsifGenerateBranch] = None, + elseBranch: ElseGenerateBranch = None, + ): + super().__init__(label, ifBranch, elsifBranches, elseBranch) DOMMixin.__init__(self, generateNode) @classmethod @@ -337,17 +344,18 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): print("if branch", generateNode, GetIirKindOfNode(generateNode)) ifBranch = IfGenerateBranch.parse(generateNode) + elsifBranches = [] + elseBranch = None # Python 3.8 syntax # elseClause = generateNode # while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: elseClause = nodes.Get_Generate_Else_Clause(generateNode) while elseClause != nodes.Null_Iir: - print("els(if) branch", elseClause, GetIirKindOfNode(elseClause)) - ifBranch = ElsifGenerateBranch.parse(generateNode) + elsifBranches.append(ElsifGenerateBranch.parse(generateNode)) elseClause = nodes.Get_Generate_Else_Clause(elseClause) - return cls(generateNode, label, ifBranch) + return cls(generateNode, label, ifBranch, elsifBranches, elseBranch) @export @@ -381,18 +389,12 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): @export -class WaveformElement( - VHDLModel_WaveformElement, DOMMixin -): - def __init__( - self, - waveformNode: Iir, - expression: Expression, - after: Expression - ): +class WaveformElement(VHDLModel_WaveformElement, DOMMixin): + def __init__(self, waveformNode: Iir, expression: Expression, after: Expression): super().__init__(expression, after) DOMMixin.__init__(self, waveformNode) + @export class ConcurrentSimpleSignalAssignment( VHDLModel_ConcurrentSimpleSignalAssignment, DOMMixin -- cgit v1.2.3 From 3abbfe34b529af865d6549bb3e6ed47ea1ab1e37 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 03:34:54 +0200 Subject: Improved handling of generate statements and pretty-printing of hierarchy. --- pyGHDL/dom/Concurrent.py | 86 ++++++++++++++++++++++++++++-------------------- 1 file changed, 51 insertions(+), 35 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 69ae8bdea..6448a748d 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -34,6 +34,7 @@ from typing import Iterable from pydecor import export +from pyGHDL.dom.Range import Range from pyVHDLModel.SyntaxModel import ( ComponentInstantiation as VHDLModel_ComponentInstantiation, EntityInstantiation as VHDLModel_EntityInstantiation, @@ -57,7 +58,7 @@ from pyVHDLModel.SyntaxModel import ( from pyGHDL.libghdl import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin -from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode +from pyGHDL.dom._Utils import GetNameOfNode @export @@ -235,7 +236,7 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): statementChain, "if-generate branch", alternativeLabel ) - return cls(body, condition, declaredItems, statements, alternativeLabel) + return cls(generateNode, condition, declaredItems, statements, alternativeLabel) @export @@ -252,14 +253,14 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): DOMMixin.__init__(self, branchNode) @classmethod - def parse(cls, generateNode: Iir) -> "ElsifGenerateBranch": + def parse(cls, generateNode: Iir, condition: Iir) -> "ElsifGenerateBranch": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetStatementsFromChainedNodes, GetExpressionFromNode, ) - condition = GetExpressionFromNode(nodes.Get_Condition(generateNode)) + condition = GetExpressionFromNode(condition) body = nodes.Get_Generate_Statement_Body(generateNode) alternativeLabelId = nodes.Get_Alternative_Label(body) @@ -267,15 +268,15 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): declarationChain = nodes.Get_Declaration_Chain(body) declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "if-generate branch", alternativeLabel + declarationChain, "elsif-generate branch", alternativeLabel ) statementChain = nodes.Get_Concurrent_Statement_Chain(body) statements = GetStatementsFromChainedNodes( - statementChain, "if-generate branch", alternativeLabel + statementChain, "elsif-generate branch", alternativeLabel ) - return cls(body, condition, declaredItems, statements, alternativeLabel) + return cls(generateNode, condition, declaredItems, statements, alternativeLabel) @export @@ -295,7 +296,6 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetStatementsFromChainedNodes, - GetExpressionFromNode, ) body = nodes.Get_Generate_Statement_Body(generateNode) @@ -305,15 +305,15 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): declarationChain = nodes.Get_Declaration_Chain(body) declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "if-generate branch", alternativeLabel + declarationChain, "else-generate branch", alternativeLabel ) statementChain = nodes.Get_Concurrent_Statement_Chain(body) statements = GetStatementsFromChainedNodes( - statementChain, "if-generate branch", alternativeLabel + statementChain, "else-generate branch", alternativeLabel ) - return cls(body, declaredItems, statements, alternativeLabel) + return cls(generateNode, declaredItems, statements, alternativeLabel) @export @@ -331,27 +331,20 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): @classmethod def parse(cls, generateNode: Iir, label: str) -> "IfGenerateStatement": - from pyGHDL.dom._Translate import ( - GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, - GetExpressionFromNode, - ) - - # TODO: get branches - # TODO: get declared items - # TODO: get concurrent statements - - print("if branch", generateNode, GetIirKindOfNode(generateNode)) ifBranch = IfGenerateBranch.parse(generateNode) - elsifBranches = [] elseBranch = None - # Python 3.8 syntax - # elseClause = generateNode - # while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: + # WORKAROUND: Python 3.8 syntax + # elseClause = generateNode + # while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: elseClause = nodes.Get_Generate_Else_Clause(generateNode) while elseClause != nodes.Null_Iir: - elsifBranches.append(ElsifGenerateBranch.parse(generateNode)) + condition = nodes.Get_Condition(elseClause) + if condition != nodes.Null_Iir: + elsifBranches.append(ElsifGenerateBranch.parse(elseClause, condition)) + else: + elseBranch = ElseGenerateBranch.parse(elseClause) + break elseClause = nodes.Get_Generate_Else_Clause(elseClause) @@ -367,25 +360,48 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): @classmethod def parse(cls, generateNode: Iir, label: str) -> "CaseGenerateStatement": # TODO: get choices - # TODO: get declared items - # TODO: get concurrent statements return cls(generateNode, label) @export class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): - def __init__(self, generateNode: Iir, label: str): - super().__init__(label) + def __init__( + self, + generateNode: Iir, + label: str, + loopIndex: str, + range: Range, + declaredItems: Iterable = None, + statements: Iterable[ConcurrentStatement] = None, + ): + super().__init__(label, loopIndex, range, declaredItems, statements) DOMMixin.__init__(self, generateNode) @classmethod def parse(cls, generateNode: Iir, label: str) -> "ForGenerateStatement": - # TODO: get index and range - # TODO: get declared items - # TODO: get concurrent statements + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + GetRangeFromNode, + ) - return cls(generateNode, label) + spec = nodes.Get_Parameter_Specification(generateNode) + loopIndex = GetNameOfNode(spec) + rng = GetRangeFromNode(nodes.Get_Discrete_Range(spec)) + + body = nodes.Get_Generate_Statement_Body(generateNode) + declarationChain = nodes.Get_Declaration_Chain(body) + declaredItems = GetDeclaredItemsFromChainedNodes( + declarationChain, "for-generate", label + ) + + statementChain = nodes.Get_Concurrent_Statement_Chain(body) + statements = GetStatementsFromChainedNodes( + statementChain, "for-generate", label + ) + + return cls(generateNode, label, loopIndex, rng, declaredItems, statements) @export -- cgit v1.2.3 From b34f3e885407693a2839771fd469af4ce2b40978 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 11:48:00 +0200 Subject: Improvements for case generate statements. --- pyGHDL/dom/Concurrent.py | 132 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 128 insertions(+), 4 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 6448a748d..f493a4c69 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -45,6 +45,10 @@ from pyVHDLModel.SyntaxModel import ( ElsifGenerateBranch as VHDLModel_ElsifGenerateBranch, ElseGenerateBranch as VHDLModel_ElseGenerateBranch, IfGenerateStatement as VHDLModel_IfGenerateStatement, + IndexedGenerateChoice as VHDLModel_IndexedGenerateChoice, + RangedGenerateChoice as VHDLModel_RangedGenerateChoice, + OthersGenerateCase as VHDLModel_OthersGenerateCase, + GenerateCase as VHDLModel_GenerateCase, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, WaveformElement as VHDLModel_WaveformElement, @@ -53,9 +57,10 @@ from pyVHDLModel.SyntaxModel import ( ConcurrentStatement, SequentialStatement, Expression, + ConcurrentChoice, ) -from pyGHDL.libghdl import Iir +from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode @@ -351,17 +356,136 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): return cls(generateNode, label, ifBranch, elsifBranches, elseBranch) +@export +class IndexedGenerateChoice(VHDLModel_IndexedGenerateChoice, DOMMixin): + def __init__(self, node: Iir, expression: Expression): + super().__init__(expression) + DOMMixin.__init__(self, node) + + +@export +class RangedGenerateChoice(VHDLModel_RangedGenerateChoice, DOMMixin): + def __init__(self, node: Iir, rng: Range): + super().__init__(rng) + DOMMixin.__init__(self, node) + + +@export +class GenerateCase(VHDLModel_GenerateCase, DOMMixin): + def __init__(self, node: Iir, choices: Iterable[ConcurrentChoice]): + super().__init__(choices) + DOMMixin.__init__(self, node) + + @classmethod + def parse(cls, caseNode: Iir) -> "GenerateCase": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + ) + + body = nodes.Get_Generate_Statement_Body(caseNode) + + alternativeLabelId = nodes.Get_Alternative_Label(body) + alternativeLabel = "" + + declarationChain = nodes.Get_Declaration_Chain(body) + declaredItems = GetDeclaredItemsFromChainedNodes( + declarationChain, "else-generate branch", alternativeLabel + ) + + statementChain = nodes.Get_Concurrent_Statement_Chain(body) + statements = GetStatementsFromChainedNodes( + statementChain, "else-generate branch", alternativeLabel + ) + + return cls(caseNode, declaredItems, statements, alternativeLabel) + + +@export +class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): + def __init__( + self, + caseNode: Iir, + declaredItems: Iterable = None, + statements: Iterable[ConcurrentStatement] = None, + alternativeLabel: str = None, + ): + super().__init__(declaredItems, statements, alternativeLabel) + DOMMixin.__init__(self, caseNode) + + @classmethod + def parse(cls, caseNode: Iir) -> "OthersGenerateCase": + from pyGHDL.dom._Translate import ( + GetDeclaredItemsFromChainedNodes, + GetStatementsFromChainedNodes, + ) + + # body = nodes.Get_Generate_Statement_Body(caseNode) + # + # alternativeLabelId = nodes.Get_Alternative_Label(body) + # alternativeLabel = "" + # + # declarationChain = nodes.Get_Declaration_Chain(body) + # declaredItems = GetDeclaredItemsFromChainedNodes( + # declarationChain, "else-generate branch", alternativeLabel + # ) + # + # statementChain = nodes.Get_Concurrent_Statement_Chain(body) + # statements = GetStatementsFromChainedNodes( + # statementChain, "else-generate branch", alternativeLabel + # ) + + # return cls(caseNode, declaredItems, statements, alternativeLabel) + return cls(caseNode, [], [], "") + + @export class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): - def __init__(self, generateNode: Iir, label: str): - super().__init__(label) + def __init__( + self, generateNode: Iir, label: str, expression: Expression, cases: Iterable + ): + super().__init__(label, expression, cases) DOMMixin.__init__(self, generateNode) @classmethod def parse(cls, generateNode: Iir, label: str) -> "CaseGenerateStatement": + from pyGHDL.dom._Translate import ( + GetExpressionFromNode, + GetIirKindOfNode, + GetRangeFromNode, + ) + # TODO: get choices - return cls(generateNode, label) + expression = GetExpressionFromNode(nodes.Get_Expression(generateNode)) + + cases = [] + choices = [] + alternatives = nodes.Get_Case_Statement_Alternative_Chain(generateNode) + for alternative in utils.chain_iter(alternatives): + choiceKind = GetIirKindOfNode(alternative) + + if choiceKind in ( + nodes.Iir_Kind.Choice_By_Name, + nodes.Iir_Kind.Choice_By_Expression, + ): + choiceExpression = GetExpressionFromNode( + nodes.Get_Choice_Expression(alternative) + ) + choices.append(IndexedGenerateChoice(alternative, choiceExpression)) + cases.append(GenerateCase(alternative, choices)) + choices = [] + elif choiceKind is nodes.Iir_Kind.Choice_By_Range: + rng = GetRangeFromNode(nodes.Get_Choice_Range(alternative)) + choices.append(RangedGenerateChoice(alternative, rng)) + cases.append(GenerateCase(alternative, choices)) + choices = [] + elif choiceKind is nodes.Iir_Kind.Choice_By_Others: + cases.append(OthersGenerateCase.parse(alternative)) + else: + print(choiceKind) + + return cls(generateNode, label, expression, cases) @export -- cgit v1.2.3 From bc09bbf10599436e1efdb0432886b2bb8b4bf890 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 15:49:39 +0200 Subject: Support for concurrent procedure call. --- pyGHDL/dom/Concurrent.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index f493a4c69..afff56747 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -53,6 +53,7 @@ from pyVHDLModel.SyntaxModel import ( ForGenerateStatement as VHDLModel_ForGenerateStatement, WaveformElement as VHDLModel_WaveformElement, ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment, + ConcurrentProcedureCall as VHDLModel_ConcurrentProcedureCall, Name, ConcurrentStatement, SequentialStatement, @@ -564,3 +565,30 @@ class ConcurrentSimpleSignalAssignment( expression = [None] return cls(assignmentNode, label, targetName, expression) + + +@export +class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): + def __init__( + self, + callNode: Iir, + label: str, + procedureName: Name, + parameterMappings: Iterable, + ): + super().__init__(label, procedureName, parameterMappings) + DOMMixin.__init__(self, callNode) + + @classmethod + def parse(cls, callNode: Iir, label: str) -> "ConcurrentProcedureCall": + from pyGHDL.dom._Translate import GetNameFromNode, GetIirKindOfNode + + call = nodes.Get_Procedure_Call(callNode) + prefix = nodes.Get_Prefix(call) + + procedureName = GetNameFromNode(prefix) + + # TODO: parameter mappings + parameterMappings = [] + + return cls(callNode, label, procedureName, parameterMappings) -- cgit v1.2.3 From 357cb9746c53e3f32fc9c2f28686c25e388918c3 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 12 Aug 2021 13:06:11 +0200 Subject: Preparations for sequential statements. --- pyGHDL/dom/Concurrent.py | 59 +++++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 28 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index afff56747..a23bb8cf6 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -58,7 +58,7 @@ from pyVHDLModel.SyntaxModel import ( ConcurrentStatement, SequentialStatement, Expression, - ConcurrentChoice, + ConcurrentChoice, ConcurrentCase, ) from pyGHDL.libghdl import Iir, utils @@ -156,13 +156,13 @@ class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): def parse(cls, blockNode: Iir, label: str) -> "ConcurrentBlockStatement": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetConcurrentStatementsFromChainedNodes, ) declaredItems = GetDeclaredItemsFromChainedNodes( nodes.Get_Declaration_Chain(blockNode), "block", label ) - statements = GetStatementsFromChainedNodes( + statements = GetConcurrentStatementsFromChainedNodes( nodes.Get_Concurrent_Statement_Chain(blockNode), "block", label ) @@ -188,19 +188,17 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): ) -> "ProcessStatement": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetSequentialStatementsFromChainedNodes, + GetIirKindOfNode ) - # TODO: get sensitivity list - # TODO: get declared items - # TODO: get sequential statements - - declaredItems = None - statements = None sensitivityList = None - if hasSensitivityList: - pass + sensitivityListNode = nodes.Get_Sensitivity_List(processNode) + print("sensi", GetIirKindOfNode(sensitivityListNode)) + + declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label) + statements = GetSequentialStatementsFromChainedNodes(nodes.Get_Sequential_Statement_Chain(processNode), "process", label) return cls(processNode, label, declaredItems, statements, sensitivityList) @@ -222,7 +220,7 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): def parse(cls, generateNode: Iir) -> "IfGenerateBranch": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetConcurrentStatementsFromChainedNodes, GetExpressionFromNode, ) @@ -238,7 +236,7 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): ) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetStatementsFromChainedNodes( + statements = GetConcurrentStatementsFromChainedNodes( statementChain, "if-generate branch", alternativeLabel ) @@ -262,7 +260,7 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): def parse(cls, generateNode: Iir, condition: Iir) -> "ElsifGenerateBranch": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetConcurrentStatementsFromChainedNodes, GetExpressionFromNode, ) @@ -278,7 +276,7 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): ) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetStatementsFromChainedNodes( + statements = GetConcurrentStatementsFromChainedNodes( statementChain, "elsif-generate branch", alternativeLabel ) @@ -301,7 +299,7 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): def parse(cls, generateNode: Iir) -> "ElseGenerateBranch": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetConcurrentStatementsFromChainedNodes, ) body = nodes.Get_Generate_Statement_Body(generateNode) @@ -315,7 +313,7 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): ) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetStatementsFromChainedNodes( + statements = GetConcurrentStatementsFromChainedNodes( statementChain, "else-generate branch", alternativeLabel ) @@ -373,7 +371,10 @@ class RangedGenerateChoice(VHDLModel_RangedGenerateChoice, DOMMixin): @export class GenerateCase(VHDLModel_GenerateCase, DOMMixin): - def __init__(self, node: Iir, choices: Iterable[ConcurrentChoice]): + def __init__(self, node: Iir, choices: Iterable[ConcurrentChoice], + declaredItems: Iterable = None, + statements: Iterable[ConcurrentStatement] = None, + alternativeLabel: str = None,): super().__init__(choices) DOMMixin.__init__(self, node) @@ -381,7 +382,7 @@ class GenerateCase(VHDLModel_GenerateCase, DOMMixin): def parse(cls, caseNode: Iir) -> "GenerateCase": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetConcurrentStatementsFromChainedNodes, ) body = nodes.Get_Generate_Statement_Body(caseNode) @@ -389,17 +390,19 @@ class GenerateCase(VHDLModel_GenerateCase, DOMMixin): alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" + choices = [] + declarationChain = nodes.Get_Declaration_Chain(body) declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "else-generate branch", alternativeLabel + declarationChain, "generate case", alternativeLabel ) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetStatementsFromChainedNodes( - statementChain, "else-generate branch", alternativeLabel + statements = GetConcurrentStatementsFromChainedNodes( + statementChain, "generate case", alternativeLabel ) - return cls(caseNode, declaredItems, statements, alternativeLabel) + return cls(caseNode, choices, declaredItems, statements, alternativeLabel) @export @@ -418,7 +421,7 @@ class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): def parse(cls, caseNode: Iir) -> "OthersGenerateCase": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetConcurrentStatementsFromChainedNodes, ) # body = nodes.Get_Generate_Statement_Body(caseNode) @@ -443,7 +446,7 @@ class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): @export class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): def __init__( - self, generateNode: Iir, label: str, expression: Expression, cases: Iterable + self, generateNode: Iir, label: str, expression: Expression, cases: Iterable[ConcurrentCase] ): super().__init__(label, expression, cases) DOMMixin.__init__(self, generateNode) @@ -507,7 +510,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): def parse(cls, generateNode: Iir, label: str) -> "ForGenerateStatement": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, - GetStatementsFromChainedNodes, + GetConcurrentStatementsFromChainedNodes, GetRangeFromNode, ) @@ -522,7 +525,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): ) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetStatementsFromChainedNodes( + statements = GetConcurrentStatementsFromChainedNodes( statementChain, "for-generate", label ) -- cgit v1.2.3 From c4326161ce97d3286e8dffe31d0c168e05f3f9ea Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 13 Aug 2021 22:21:04 +0200 Subject: Improved handling of ranges (e.g. via attribute names). --- pyGHDL/dom/Concurrent.py | 50 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 7 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index a23bb8cf6..de4e70539 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -58,12 +58,13 @@ from pyVHDLModel.SyntaxModel import ( ConcurrentStatement, SequentialStatement, Expression, - ConcurrentChoice, ConcurrentCase, + ConcurrentChoice, + ConcurrentCase, ) from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes -from pyGHDL.dom import DOMMixin +from pyGHDL.dom import DOMMixin, DOMException, Position from pyGHDL.dom._Utils import GetNameOfNode @@ -186,10 +187,10 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): def parse( cls, processNode: Iir, label: str, hasSensitivityList: bool ) -> "ProcessStatement": + from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes, - GetIirKindOfNode ) sensitivityList = None @@ -453,10 +454,11 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): @classmethod def parse(cls, generateNode: Iir, label: str) -> "CaseGenerateStatement": + from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom._Translate import ( GetExpressionFromNode, - GetIirKindOfNode, GetRangeFromNode, + GetNameFromNode, ) # TODO: get choices @@ -480,7 +482,23 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): cases.append(GenerateCase(alternative, choices)) choices = [] elif choiceKind is nodes.Iir_Kind.Choice_By_Range: - rng = GetRangeFromNode(nodes.Get_Choice_Range(alternative)) + choiceRange = nodes.Get_Choice_Range(alternative) + choiceRangeKind = GetIirKindOfNode(choiceRange) + if choiceRangeKind == nodes.Iir_Kind.Range_Expression: + rng = GetRangeFromNode(choiceRange) + elif choiceRangeKind in ( + nodes.Iir_Kind.Attribute_Name, + nodes.Iir_Kind.Parenthesis_Name, + ): + rng = GetNameFromNode(choiceRange) + else: + pos = Position.parse(generateNode) + raise DOMException( + "Unknown choice range kind '{kind}' in case...generate statement at line {line}.".format( + kind=choiceRangeKind.name, line=pos.Line + ) + ) + choices.append(RangedGenerateChoice(alternative, rng)) cases.append(GenerateCase(alternative, choices)) choices = [] @@ -508,15 +526,33 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): @classmethod def parse(cls, generateNode: Iir, label: str) -> "ForGenerateStatement": + from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, GetRangeFromNode, + GetNameFromNode, ) spec = nodes.Get_Parameter_Specification(generateNode) loopIndex = GetNameOfNode(spec) - rng = GetRangeFromNode(nodes.Get_Discrete_Range(spec)) + + discreteRange = nodes.Get_Discrete_Range(spec) + rangeKind = GetIirKindOfNode(discreteRange) + if rangeKind == nodes.Iir_Kind.Range_Expression: + rng = GetRangeFromNode(discreteRange) + elif rangeKind in ( + nodes.Iir_Kind.Attribute_Name, + nodes.Iir_Kind.Parenthesis_Name, + ): + rng = GetNameFromNode(discreteRange) + else: + pos = Position.parse(generateNode) + raise DOMException( + "Unknown discete range kind '{kind}' in for...generate statement at line {line}.".format( + kind=rangeKind.name, line=pos.Line + ) + ) body = nodes.Get_Generate_Statement_Body(generateNode) declarationChain = nodes.Get_Declaration_Chain(body) @@ -584,7 +620,7 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): @classmethod def parse(cls, callNode: Iir, label: str) -> "ConcurrentProcedureCall": - from pyGHDL.dom._Translate import GetNameFromNode, GetIirKindOfNode + from pyGHDL.dom._Translate import GetNameFromNode call = nodes.Get_Procedure_Call(callNode) prefix = nodes.Get_Prefix(call) -- cgit v1.2.3 From edd59b8997c30c8a559d4d7d433631ef03c19546 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 13 Aug 2021 22:36:41 +0200 Subject: Black formatting. --- pyGHDL/dom/Concurrent.py | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index de4e70539..685d02287 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -196,10 +196,14 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): sensitivityList = None if hasSensitivityList: sensitivityListNode = nodes.Get_Sensitivity_List(processNode) - print("sensi", GetIirKindOfNode(sensitivityListNode)) + # print("sensi", GetIirKindOfNode(sensitivityListNode)) - declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label) - statements = GetSequentialStatementsFromChainedNodes(nodes.Get_Sequential_Statement_Chain(processNode), "process", label) + declaredItems = GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(processNode), "process", label + ) + statements = GetSequentialStatementsFromChainedNodes( + nodes.Get_Sequential_Statement_Chain(processNode), "process", label + ) return cls(processNode, label, declaredItems, statements, sensitivityList) @@ -372,10 +376,14 @@ class RangedGenerateChoice(VHDLModel_RangedGenerateChoice, DOMMixin): @export class GenerateCase(VHDLModel_GenerateCase, DOMMixin): - def __init__(self, node: Iir, choices: Iterable[ConcurrentChoice], + def __init__( + self, + node: Iir, + choices: Iterable[ConcurrentChoice], declaredItems: Iterable = None, statements: Iterable[ConcurrentStatement] = None, - alternativeLabel: str = None,): + alternativeLabel: str = None, + ): super().__init__(choices) DOMMixin.__init__(self, node) @@ -447,7 +455,11 @@ class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): @export class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): def __init__( - self, generateNode: Iir, label: str, expression: Expression, cases: Iterable[ConcurrentCase] + self, + generateNode: Iir, + label: str, + expression: Expression, + cases: Iterable[ConcurrentCase], ): super().__init__(label, expression, cases) DOMMixin.__init__(self, generateNode) -- cgit v1.2.3 From 9d3e58db06faa9e204606b8ea6e7fc6cca6dbbab Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 14 Aug 2021 21:40:38 +0200 Subject: Handle multiple choices per case. --- pyGHDL/dom/Concurrent.py | 52 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 11 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 685d02287..3b1f22829 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -478,10 +478,13 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): expression = GetExpressionFromNode(nodes.Get_Expression(generateNode)) cases = [] - choices = [] - alternatives = nodes.Get_Case_Statement_Alternative_Chain(generateNode) - for alternative in utils.chain_iter(alternatives): + choices = None + alternative = nodes.Get_Case_Statement_Alternative_Chain(generateNode) + + while alternative != nodes.Null_Iir: choiceKind = GetIirKindOfNode(alternative) + sameAlternative = nodes.Get_Same_Alternative_Flag(alternative) + print("sameAlternative: ", sameAlternative) if choiceKind in ( nodes.Iir_Kind.Choice_By_Name, @@ -490,9 +493,12 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): choiceExpression = GetExpressionFromNode( nodes.Get_Choice_Expression(alternative) ) - choices.append(IndexedGenerateChoice(alternative, choiceExpression)) - cases.append(GenerateCase(alternative, choices)) - choices = [] + + choice = IndexedGenerateChoice(alternative, choiceExpression) + if sameAlternative: + choices.append(choice) + alternative = nodes.Get_Chain(alternative) + continue elif choiceKind is nodes.Iir_Kind.Choice_By_Range: choiceRange = nodes.Get_Choice_Range(alternative) choiceRangeKind = GetIirKindOfNode(choiceRange) @@ -504,20 +510,44 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): ): rng = GetNameFromNode(choiceRange) else: - pos = Position.parse(generateNode) + pos = Position.parse(alternative) raise DOMException( "Unknown choice range kind '{kind}' in case...generate statement at line {line}.".format( kind=choiceRangeKind.name, line=pos.Line ) ) - choices.append(RangedGenerateChoice(alternative, rng)) - cases.append(GenerateCase(alternative, choices)) - choices = [] + choice = RangedGenerateChoice(alternative, rng) + if sameAlternative: + choices.append(choice) + alternative = nodes.Get_Chain(alternative) + continue elif choiceKind is nodes.Iir_Kind.Choice_By_Others: + if choices is not None: + cases.append(GenerateCase(alternative, choices)) + choices = None cases.append(OthersGenerateCase.parse(alternative)) + alternative = nodes.Get_Chain(alternative) + continue else: - print(choiceKind) + pos = Position.parse(alternative) + raise DOMException( + "Unknown choice kind '{kind}' in case...generate statement at line {line}.".format( + kind=choiceKind.name, line=pos.Line + ) + ) + + if choices is not None: + cases.append(GenerateCase(alternative, choices)) + + choices = [ + choice, + ] + + alternative = nodes.Get_Chain(alternative) + + if choices is not None: + cases.append(GenerateCase(alternative, choices)) return cls(generateNode, label, expression, cases) -- cgit v1.2.3 From 0562c182aba6e99cbdeb302f6efa584d6642267f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 14 Aug 2021 21:58:48 +0200 Subject: Handle bodies in case generate statements. --- pyGHDL/dom/Concurrent.py | 52 +++++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 25 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 3b1f22829..b411553c5 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -384,23 +384,23 @@ class GenerateCase(VHDLModel_GenerateCase, DOMMixin): statements: Iterable[ConcurrentStatement] = None, alternativeLabel: str = None, ): - super().__init__(choices) + super().__init__(choices, declaredItems, statements, alternativeLabel) DOMMixin.__init__(self, node) @classmethod - def parse(cls, caseNode: Iir) -> "GenerateCase": + def parse( + cls, caseNode: Iir, choices: Iterable[ConcurrentChoice] + ) -> "GenerateCase": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, ) - body = nodes.Get_Generate_Statement_Body(caseNode) + body = nodes.Get_Associated_Block(caseNode) alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" - choices = [] - declarationChain = nodes.Get_Declaration_Chain(body) declaredItems = GetDeclaredItemsFromChainedNodes( declarationChain, "generate case", alternativeLabel @@ -433,23 +433,22 @@ class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): GetConcurrentStatementsFromChainedNodes, ) - # body = nodes.Get_Generate_Statement_Body(caseNode) - # - # alternativeLabelId = nodes.Get_Alternative_Label(body) - # alternativeLabel = "" - # - # declarationChain = nodes.Get_Declaration_Chain(body) - # declaredItems = GetDeclaredItemsFromChainedNodes( - # declarationChain, "else-generate branch", alternativeLabel - # ) - # - # statementChain = nodes.Get_Concurrent_Statement_Chain(body) - # statements = GetStatementsFromChainedNodes( - # statementChain, "else-generate branch", alternativeLabel - # ) - - # return cls(caseNode, declaredItems, statements, alternativeLabel) - return cls(caseNode, [], [], "") + body = nodes.Get_Associated_Block(caseNode) + + alternativeLabelId = nodes.Get_Alternative_Label(body) + alternativeLabel = "" + + declarationChain = nodes.Get_Declaration_Chain(body) + declaredItems = GetDeclaredItemsFromChainedNodes( + declarationChain, "case-generate others", alternativeLabel + ) + + statementChain = nodes.Get_Concurrent_Statement_Chain(body) + statements = GetConcurrentStatementsFromChainedNodes( + statementChain, "case-generate others", alternativeLabel + ) + + return cls(caseNode, declaredItems, statements, alternativeLabel) @export @@ -480,6 +479,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): cases = [] choices = None alternative = nodes.Get_Case_Statement_Alternative_Chain(generateNode) + caseNode = alternative while alternative != nodes.Null_Iir: choiceKind = GetIirKindOfNode(alternative) @@ -524,10 +524,11 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): continue elif choiceKind is nodes.Iir_Kind.Choice_By_Others: if choices is not None: - cases.append(GenerateCase(alternative, choices)) + cases.append(GenerateCase.parse(caseNode, choices)) choices = None cases.append(OthersGenerateCase.parse(alternative)) alternative = nodes.Get_Chain(alternative) + caseNode = alternative continue else: pos = Position.parse(alternative) @@ -538,8 +539,9 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): ) if choices is not None: - cases.append(GenerateCase(alternative, choices)) + cases.append(GenerateCase.parse(caseNode, choices)) + caseNode = alternative choices = [ choice, ] @@ -547,7 +549,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): alternative = nodes.Get_Chain(alternative) if choices is not None: - cases.append(GenerateCase(alternative, choices)) + cases.append(GenerateCase.parse(caseNode, choices)) return cls(generateNode, label, expression, cases) -- cgit v1.2.3 From db48ba4042769646676f7ffb981149cbb5e52740 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 16 Aug 2021 18:06:59 +0200 Subject: Implemented if, case and for-loop statements. --- pyGHDL/dom/Concurrent.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index b411553c5..953d4d6e3 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -232,6 +232,7 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): condition = GetExpressionFromNode(nodes.Get_Condition(generateNode)) body = nodes.Get_Generate_Statement_Body(generateNode) + # TODO: alternative label alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" @@ -272,6 +273,7 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): condition = GetExpressionFromNode(condition) body = nodes.Get_Generate_Statement_Body(generateNode) + # TODO: alternative label alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" @@ -309,6 +311,7 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): body = nodes.Get_Generate_Statement_Body(generateNode) + # TODO: alternative label alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" @@ -398,6 +401,7 @@ class GenerateCase(VHDLModel_GenerateCase, DOMMixin): body = nodes.Get_Associated_Block(caseNode) + # TODO: alternative label alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" @@ -435,6 +439,7 @@ class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): body = nodes.Get_Associated_Block(caseNode) + # TODO: alternative label alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" @@ -472,8 +477,6 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): GetNameFromNode, ) - # TODO: get choices - expression = GetExpressionFromNode(nodes.Get_Expression(generateNode)) cases = [] @@ -524,7 +527,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): continue elif choiceKind is nodes.Iir_Kind.Choice_By_Others: if choices is not None: - cases.append(GenerateCase.parse(caseNode, choices)) + cases.append(GenerateCase.parse(alternative, choices)) choices = None cases.append(OthersGenerateCase.parse(alternative)) alternative = nodes.Get_Chain(alternative) -- cgit v1.2.3 From 3f0308a5f807269aa5691fa1c704c0e9147d45f1 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 16 Aug 2021 23:47:04 +0200 Subject: Handle contexts. --- pyGHDL/dom/Concurrent.py | 1 - 1 file changed, 1 deletion(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 953d4d6e3..f4ded4e80 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -487,7 +487,6 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): while alternative != nodes.Null_Iir: choiceKind = GetIirKindOfNode(alternative) sameAlternative = nodes.Get_Same_Alternative_Flag(alternative) - print("sameAlternative: ", sameAlternative) if choiceKind in ( nodes.Iir_Kind.Choice_By_Name, -- cgit v1.2.3 From f8d7ac62564e4bdefb35e58178c4df1b4feae844 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 17 Aug 2021 13:30:49 +0200 Subject: Handle simple sequential signal assignments and it's waveforms. --- pyGHDL/dom/Concurrent.py | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index f4ded4e80..f4681dbf9 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -616,9 +616,23 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): @export class WaveformElement(VHDLModel_WaveformElement, DOMMixin): - def __init__(self, waveformNode: Iir, expression: Expression, after: Expression): + def __init__(self, waveNode: Iir, expression: Expression, after: Expression): super().__init__(expression, after) - DOMMixin.__init__(self, waveformNode) + DOMMixin.__init__(self, waveNode) + + @classmethod + def parse(cls, waveNode: Iir): + from pyGHDL.dom._Translate import GetExpressionFromNode + + value = GetExpressionFromNode(nodes.Get_We_Value(waveNode)) + + timeNode = nodes.Get_Time(waveNode) + if timeNode is nodes.Null_Iir: + time = None + else: + time = GetExpressionFromNode(timeNode) + + return cls(waveNode, value, time) @export @@ -644,12 +658,11 @@ class ConcurrentSimpleSignalAssignment( target = nodes.Get_Target(assignmentNode) targetName = GetNameFromNode(target) - waveform = nodes.Get_Waveform_Chain(assignmentNode) - - # TODO: translate waveforms to series of "expressions". - expression = [None] + waveform = [] + for wave in utils.chain_iter(nodes.Get_Waveform_Chain(assignmentNode)): + waveform.append(WaveformElement.parse(wave)) - return cls(assignmentNode, label, targetName, expression) + return cls(assignmentNode, label, targetName, waveform) @export -- cgit v1.2.3 From 8c0f8e0ad95c53beac983546550222117c6a639c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 17 Aug 2021 20:14:13 +0200 Subject: Handle associations. --- pyGHDL/dom/Concurrent.py | 142 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 116 insertions(+), 26 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index f4681dbf9..2910e596c 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -36,6 +36,9 @@ from pydecor import export from pyGHDL.dom.Range import Range from pyVHDLModel.SyntaxModel import ( + GenericAssociationItem as VHDLModel_GenericAssociationItem, + PortAssociationItem as VHDLModel_PortAssociationItem, + ParameterAssociationItem as VHDLModel_ParameterAssociationItem, ComponentInstantiation as VHDLModel_ComponentInstantiation, EntityInstantiation as VHDLModel_EntityInstantiation, ConfigurationInstantiation as VHDLModel_ConfigurationInstantiation, @@ -60,6 +63,7 @@ from pyVHDLModel.SyntaxModel import ( Expression, ConcurrentChoice, ConcurrentCase, + AssociationItem, ) from pyGHDL.libghdl import Iir, utils @@ -68,24 +72,65 @@ from pyGHDL.dom import DOMMixin, DOMException, Position from pyGHDL.dom._Utils import GetNameOfNode +@export +class GenericAssociationItem(VHDLModel_GenericAssociationItem, DOMMixin): + def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None): + super().__init__(actual, formal) + DOMMixin.__init__(self, associationNode) + + +@export +class PortAssociationItem(VHDLModel_PortAssociationItem, DOMMixin): + def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None): + super().__init__(actual, formal) + DOMMixin.__init__(self, associationNode) + + +@export +class ParameterAssociationItem(VHDLModel_ParameterAssociationItem, DOMMixin): + def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None): + super().__init__(actual, formal) + DOMMixin.__init__(self, associationNode) + + @export class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): - def __init__(self, instantiationNode: Iir, label: str, componentName: Name): - super().__init__(label, componentName) + def __init__( + self, + instantiationNode: Iir, + label: str, + componentName: Name, + genericAssociations: Iterable[AssociationItem] = None, + portAssociations: Iterable[AssociationItem] = None, + ): + super().__init__(label, componentName, genericAssociations, portAssociations) DOMMixin.__init__(self, instantiationNode) @classmethod def parse( cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str ) -> "ComponentInstantiation": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import ( + GetNameFromNode, + GetGenericMapAspect, + GetPortMapAspect, + ) componentName = GetNameFromNode(instantiatedUnit) + genericAssociations = GetGenericMapAspect( + nodes.Get_Generic_Map_Aspect_Chain(instantiationNode) + ) + portAssociations = GetPortMapAspect( + nodes.Get_Port_Map_Aspect_Chain(instantiationNode) + ) - # TODO: get mapped generics - # TODO: get mapped ports - - return cls(instantiationNode, label, componentName) + return cls( + instantiationNode, + label, + componentName, + genericAssociations, + portAssociations, + ) @export @@ -96,15 +141,23 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): label: str, entityName: Name, architectureName: Name = None, + genericAssociations: Iterable[AssociationItem] = None, + portAssociations: Iterable[AssociationItem] = None, ): - super().__init__(label, entityName, architectureName) + super().__init__( + label, entityName, architectureName, genericAssociations, portAssociations + ) DOMMixin.__init__(self, instantiationNode) @classmethod def parse( cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str ) -> "EntityInstantiation": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import ( + GetNameFromNode, + GetGenericMapAspect, + GetPortMapAspect, + ) entityId = nodes.Get_Entity_Name(instantiatedUnit) entityName = GetNameFromNode(entityId) @@ -114,31 +167,65 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): if architectureId != nodes.Null_Iir: architectureName = GetNameOfNode(architectureId) - # TODO: get mapped generics - # TODO: get mapped ports + genericAssociations = GetGenericMapAspect( + nodes.Get_Generic_Map_Aspect_Chain(instantiationNode) + ) + portAssociations = GetPortMapAspect( + nodes.Get_Port_Map_Aspect_Chain(instantiationNode) + ) - return cls(instantiationNode, label, entityName, architectureName) + return cls( + instantiationNode, + label, + entityName, + architectureName, + genericAssociations, + portAssociations, + ) @export class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin): - def __init__(self, instantiationNode: Iir, label: str, configurationName: Name): - super().__init__(label, configurationName) + def __init__( + self, + instantiationNode: Iir, + label: str, + configurationName: Name, + genericAssociations: Iterable[AssociationItem] = None, + portAssociations: Iterable[AssociationItem] = None, + ): + super().__init__( + label, configurationName, genericAssociations, portAssociations + ) DOMMixin.__init__(self, instantiationNode) @classmethod def parse( cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str ) -> "ConfigurationInstantiation": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import ( + GetNameFromNode, + GetGenericMapAspect, + GetPortMapAspect, + ) configurationId = nodes.Get_Configuration_Name(instantiatedUnit) configurationName = GetNameFromNode(configurationId) - # TODO: get mapped generics - # TODO: get mapped ports + genericAssociations = GetGenericMapAspect( + nodes.Get_Generic_Map_Aspect_Chain(instantiationNode) + ) + portAssociations = GetPortMapAspect( + nodes.Get_Port_Map_Aspect_Chain(instantiationNode) + ) - return cls(instantiationNode, label, configurationName) + return cls( + instantiationNode, + label, + configurationName, + genericAssociations, + portAssociations, + ) @export @@ -160,6 +247,9 @@ class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): GetConcurrentStatementsFromChainedNodes, ) + # genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) + # portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) + declaredItems = GetDeclaredItemsFromChainedNodes( nodes.Get_Declaration_Chain(blockNode), "block", label ) @@ -678,15 +768,15 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): DOMMixin.__init__(self, callNode) @classmethod - def parse(cls, callNode: Iir, label: str) -> "ConcurrentProcedureCall": - from pyGHDL.dom._Translate import GetNameFromNode + def parse(cls, concurrentCallNode: Iir, label: str) -> "ConcurrentProcedureCall": + from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect - call = nodes.Get_Procedure_Call(callNode) - prefix = nodes.Get_Prefix(call) + callNode = nodes.Get_Procedure_Call(concurrentCallNode) + prefix = nodes.Get_Prefix(callNode) procedureName = GetNameFromNode(prefix) + parameterAssociations = GetParameterMapAspect( + nodes.Get_Parameter_Association_Chain(callNode) + ) - # TODO: parameter mappings - parameterMappings = [] - - return cls(callNode, label, procedureName, parameterMappings) + return cls(concurrentCallNode, label, procedureName, parameterAssociations) -- cgit v1.2.3 From 8fb4da723067b2ff99050f9ef9fc0bbd3c835ef4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 23 Aug 2021 00:13:43 +0200 Subject: Some fixes. --- pyGHDL/dom/Concurrent.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 2910e596c..a1949c86b 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -277,7 +277,6 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): def parse( cls, processNode: Iir, label: str, hasSensitivityList: bool ) -> "ProcessStatement": - from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes, @@ -285,6 +284,7 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): sensitivityList = None if hasSensitivityList: + # FIXME: sensitity list sensitivityListNode = nodes.Get_Sensitivity_List(processNode) # print("sensi", GetIirKindOfNode(sensitivityListNode)) @@ -323,7 +323,7 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): body = nodes.Get_Generate_Statement_Body(generateNode) # TODO: alternative label - alternativeLabelId = nodes.Get_Alternative_Label(body) + # alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) @@ -364,7 +364,7 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): body = nodes.Get_Generate_Statement_Body(generateNode) # TODO: alternative label - alternativeLabelId = nodes.Get_Alternative_Label(body) + # alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) @@ -402,7 +402,7 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): body = nodes.Get_Generate_Statement_Body(generateNode) # TODO: alternative label - alternativeLabelId = nodes.Get_Alternative_Label(body) + # alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) @@ -492,7 +492,7 @@ class GenerateCase(VHDLModel_GenerateCase, DOMMixin): body = nodes.Get_Associated_Block(caseNode) # TODO: alternative label - alternativeLabelId = nodes.Get_Alternative_Label(body) + # alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) @@ -530,7 +530,7 @@ class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): body = nodes.Get_Associated_Block(caseNode) # TODO: alternative label - alternativeLabelId = nodes.Get_Alternative_Label(body) + # alternativeLabelId = nodes.Get_Alternative_Label(body) alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) @@ -653,11 +653,11 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): generateNode: Iir, label: str, loopIndex: str, - range: Range, + rng: Range, declaredItems: Iterable = None, statements: Iterable[ConcurrentStatement] = None, ): - super().__init__(label, loopIndex, range, declaredItems, statements) + super().__init__(label, loopIndex, rng, declaredItems, statements) DOMMixin.__init__(self, generateNode) @classmethod -- cgit v1.2.3 From 8b98e2883b40b00922c9944c2470211ee055a9a5 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 23 Aug 2021 09:02:47 +0200 Subject: Fixes due to a bug in pyVHDLModel. Name Context was used twice. --- pyGHDL/dom/Concurrent.py | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index a1949c86b..740802d18 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -60,7 +60,7 @@ from pyVHDLModel.SyntaxModel import ( Name, ConcurrentStatement, SequentialStatement, - Expression, + ExpressionUnion, ConcurrentChoice, ConcurrentCase, AssociationItem, @@ -74,21 +74,27 @@ from pyGHDL.dom._Utils import GetNameOfNode @export class GenericAssociationItem(VHDLModel_GenericAssociationItem, DOMMixin): - def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None): + def __init__( + self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None + ): super().__init__(actual, formal) DOMMixin.__init__(self, associationNode) @export class PortAssociationItem(VHDLModel_PortAssociationItem, DOMMixin): - def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None): + def __init__( + self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None + ): super().__init__(actual, formal) DOMMixin.__init__(self, associationNode) @export class ParameterAssociationItem(VHDLModel_ParameterAssociationItem, DOMMixin): - def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None): + def __init__( + self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None + ): super().__init__(actual, formal) DOMMixin.__init__(self, associationNode) @@ -303,7 +309,7 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): def __init__( self, branchNode: Iir, - condition: Expression, + condition: ExpressionUnion, declaredItems: Iterable = None, statements: Iterable[ConcurrentStatement] = None, alternativeLabel: str = None, @@ -344,7 +350,7 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): def __init__( self, branchNode: Iir, - condition: Expression, + condition: ExpressionUnion, declaredItems: Iterable = None, statements: Iterable[ConcurrentStatement] = None, alternativeLabel: str = None, @@ -455,7 +461,7 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): @export class IndexedGenerateChoice(VHDLModel_IndexedGenerateChoice, DOMMixin): - def __init__(self, node: Iir, expression: Expression): + def __init__(self, node: Iir, expression: ExpressionUnion): super().__init__(expression) DOMMixin.__init__(self, node) @@ -552,7 +558,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): self, generateNode: Iir, label: str, - expression: Expression, + expression: ExpressionUnion, cases: Iterable[ConcurrentCase], ): super().__init__(label, expression, cases) @@ -706,7 +712,9 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): @export class WaveformElement(VHDLModel_WaveformElement, DOMMixin): - def __init__(self, waveNode: Iir, expression: Expression, after: Expression): + def __init__( + self, waveNode: Iir, expression: ExpressionUnion, after: ExpressionUnion + ): super().__init__(expression, after) DOMMixin.__init__(self, waveNode) -- cgit v1.2.3 From b229fa55b6485350ced8e31d6a803d08544b6d22 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 23 Aug 2021 15:41:10 +0200 Subject: Skip null statement. --- pyGHDL/dom/Concurrent.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 740802d18..e7162cc81 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -290,8 +290,9 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): sensitivityList = None if hasSensitivityList: + pass # FIXME: sensitity list - sensitivityListNode = nodes.Get_Sensitivity_List(processNode) + # sensitivityListNode = nodes.Get_Sensitivity_List(processNode) # print("sensi", GetIirKindOfNode(sensitivityListNode)) declaredItems = GetDeclaredItemsFromChainedNodes( -- cgit v1.2.3