From fe9e78d4360d31ed3f8b1873195e7f84b96ebfc2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 14 Sep 2021 04:14:03 +0200
Subject: synth-vhdl_oper: handle nor for boolean
---
src/synth/synth-vhdl_oper.adb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb
index 69213e9f9..d7d73bcec 100644
--- a/src/synth/synth-vhdl_oper.adb
+++ b/src/synth/synth-vhdl_oper.adb
@@ -788,6 +788,7 @@ package body Synth.Vhdl_Oper is
| Iir_Predefined_Ieee_1164_Scalar_Or =>
return Synth_Bit_Dyadic (Id_Or);
when Iir_Predefined_Bit_Nor
+ | Iir_Predefined_Boolean_Nor
| Iir_Predefined_Ieee_1164_Scalar_Nor =>
return Synth_Bit_Dyadic (Id_Nor);
when Iir_Predefined_Bit_Nand
--
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