From fc713626e51847a501c22c5b7d6dfda88e1d0183 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 22 Dec 2016 06:55:04 +0100 Subject: issue43: add a file. --- testsuite/gna/issue43/repro3.vhdl | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 testsuite/gna/issue43/repro3.vhdl diff --git a/testsuite/gna/issue43/repro3.vhdl b/testsuite/gna/issue43/repro3.vhdl new file mode 100644 index 000000000..ea43dd53e --- /dev/null +++ b/testsuite/gna/issue43/repro3.vhdl @@ -0,0 +1,24 @@ +entity test_tb is +end entity; + +architecture beh of test_tb is + signal rx_data : bit_vector(159 downto 0); + + procedure to_t( signal sa : out bit_vector(31 downto 0)) is + begin + sa <= (others => '1'); + assert false report "lol"; + end procedure; +begin + asd : for i in 0 to 4 generate + begin + process + subtype rng1 is natural range 32*(i+1)-1 downto 32*i; + begin + wait for 10 ns; + to_t(rx_data(rng1)); + wait; + end process; + end generate; + +end architecture; -- cgit v1.2.3