From f721c20920414f86d97e025aea8587e116368471 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 19 Apr 2023 20:54:41 +0200
Subject: testsuite/synth: add a test for #2418

---
 testsuite/synth/issue2418/ent.vhdl     | 21 +++++++++++++++++++++
 testsuite/synth/issue2418/testsuite.sh |  7 +++++++
 2 files changed, 28 insertions(+)
 create mode 100644 testsuite/synth/issue2418/ent.vhdl
 create mode 100755 testsuite/synth/issue2418/testsuite.sh

diff --git a/testsuite/synth/issue2418/ent.vhdl b/testsuite/synth/issue2418/ent.vhdl
new file mode 100644
index 000000000..b3ffd064a
--- /dev/null
+++ b/testsuite/synth/issue2418/ent.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+    port (
+        sel : in std_logic_vector(1 downto 0)
+    );
+end entity ent;
+
+architecture arch of ent is
+    signal reg : std_logic_vector(7 downto 0);
+begin
+    process(sel)
+    begin
+        reg <= (others => '0');
+
+        -- This is the line that causes the error
+        reg(to_integer(unsigned(sel)) + 1 downto to_integer(unsigned(sel))) <= (others => '1');
+    end process;
+end architecture arch;
diff --git a/testsuite/synth/issue2418/testsuite.sh b/testsuite/synth/issue2418/testsuite.sh
new file mode 100755
index 000000000..08ebf93a4
--- /dev/null
+++ b/testsuite/synth/issue2418/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only ent
+
+echo "Test successful"
-- 
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